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PDF ( 数据手册 , 数据表 ) 82374SB

零件编号 82374SB
描述 SYSTEM COMPONENT (ESC)
制造商 Intel Corporation
LOGO Intel Corporation LOGO 


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82374SB 数据手册, 描述, 功能
82374EB 82374SB EISA
SYSTEM COMPONENT (ESC)
Y Integrates EISA Compatible Bus
Controller
Translates Cycles Between EISA and
ISA Bus
Supports EISA Burst and Standard
Cycles
Supports ISA Zero Wait-State Cycles
Supports Byte Assembly
Disassembly for 8- 16- and 32-Bit
Transfers
Supports EISA Bus Frequency of up
to 8 33 MHz
Y Supports Eight EISA Slots
Directly Drives Address Data and
Control Signals for Eight Slots
Decodes Address for Eight Slot
Specific AENs
Y Provides Enhanced DMA Controller
Provides Scatter-Gather Function
Supports Type A Type B Type C
(Burst) and Compatible DMA
Transfer
Provides Seven Independently
Programmable Channels
Integrates Two 82C37A Compatible
DMA Controllers
Y Integrates the Functionality of two
82C59 Interrupt Controllers and two
82C54 Timers
Provides 14 Programmable Channels
for Edge or Level Interrupts
Provides 4 PCI Interrupts Routible to
any of 11 Interrupt Channels
Supports Timer Function for Refresh
Request System Timer Speaker
Tone Fail Safe Timer and CPU
Speed Control
Y Advanced Programmable Interrupt
Controller (APIC)
Multiprocessor Interrupt
Management
Separate Bus For Interrupt Messages
Y 5V CMOS Technology
Y Provides High Performance Arbitration
Supports Eight EISA Masters and
PCEB
Supports ISA Masters DMA
Channels and Refresh
Provides Programmable Arbitration
Scheme for Fixed Rotating or
Combination Priority
Y Integrates Support Logic for X-Bus
Peripherals
Generates Chip Selects Encoded
Chip Selects for Floppy and
Keyboard Controller IDE Parallel
Serial Ports and General Purpose
Peripherals
Provides Interface for Real Time
Clock
Generates Control Signals for X-Bus
Data Transceiver
Integrates Port 92 Mouse Interrupt
and Coprocessor Error Reporting
Y Generates Non-Maskable Interrupts
(NMI)
PCI System Errors
PCI Parity Errors
EISA Bus Parity Errors
Fail Safe Timer
Bus Timeout
Via Software Control
Y Provides BIOS Interface
Supports 512K Bytes of Flash or
EPROM BIOS on the X-Bus
Allows BIOS on PCI
Supports Integrated VGA BIOS
Y 82374SB System Power Management
(Intel SMM Support)
Fast On Off Support via SMI
GenerationHardware Events
Software Events EXTSMI Fast Off
Timer System Events
Programmable CPU Clock Control
Enables Energy Efficient Desktop
Systems
Y Only Available as Part of a Supported
Kit
Y 208-Pin QFP Package
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
March 1996
Order Number 290476-004







82374SB pdf, 数据表
CONTENTS
5 9 EISA Slot Support
5 9 1 AEN GENERATION
5 9 2 MACKX GENERATION
6 0 DMA CONTROLLER
6 1 DMA Controller Overview
6 2 DMA Transfer Modes
6 2 1 SINGLE TRANSFER MODE
6 2 2 BLOCK TRANSFER MODE
6 2 3 DEMAND TRANSFER MODE
6 2 4 CASCADE MODE
6 3 DMA Transfer Types
6 4 DMA Timing
6 4 1 COMPATIBLE TIMINGS
6 4 2 TYPE ‘‘A’’ TIMING
6 4 3 TYPE ‘‘B’’ TIMING
6 4 4 TYPE ‘‘C’’ (BURST) TIMING
6 5 Channel Priority
6 6 Scatter-Gather Functional Description
6 7 Register Functionality
6 7 1 ADDRESS COMPATIBILITY MODE
6 7 2 SUMMARY OF THE DMA TRANSFER SIZES
6 7 3 ADDRESS SHIFTING WHEN PROGRAMMED FOR 16-BIT I O COUNT BY
WORDS
6 7 4 STOP REGISTERS (RING BUFFER DATA STRUCTURE)
6 7 5 BUFFER CHAINING MODE AND STATUS REGISTERS
6 7 6 AUTOINITIALIZE
6 8 Software Commands
6 8 1 CLEAR BYTE POINTER FLIP-FLOP
6 8 2 DMA MASTER CLEAR
6 8 3 CLEAR MASK REGISTER
6 9 Terminal Count EOP Summary
6 10 Buffer Chaining
6 11 Refresh Unit
7 0 EISA BUS ARBITRATION
7 1 Arbitration Priority
7 2 Preemption
7 2 1 PCEB EISA BUS ACQUISITION AND PCEB PREEMPTION
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82374SB equivalent, schematic
82374EB 82374SB
By using burst transactions to fill or flush these buffers if appropriate the PCEB maximizes bus efficiency For
example an EISA device could fill a Line Buffer with byte word or Dword transfers and The PCEB would use a
PCI burst cycle to flush the filled line to PCI memory
BIOS Timer
The PCEB has a 16 bit BIOS Timer The timer can be used by BIOS software to implement timing loops The
timer count rate is derived from the EISA clock (BCLK) and has an accuracy of g 1 ms
1 2 ESC Overview
The ESC implements system functions (e g timer counter DMA and interrupt controller) and EISA subsys-
tem control functions (e g EISA bus controller and EISA bus arbiter) The major functions provided by the
ESC are described in this section
EISA Controller
The ESC incorporates a 32-bit master and an 8-bit slave The ESC directly drives eight EISA slots without
external data or address buffering EISA system clock (BCLK) generation is integrated by dividing the PCI
clock (divide by 3 or divide by 4) and wait-state generation is provided The AENx and MACKx signals provide
a direct interface to four EISA slots and supports eight EISA slots with encoded AENx and MACKx signals
The ESC contains an 8-bit data bus (lower 8 bits of the EISA data bus) that is used to program the ESC’s
internal registers Note that for transfers between the PCI and EISA Buses the PCEB provides the data path
Thus the ESC does not require a full 32 bit data bus A full 32-bit address bus is provided and is used during
refresh cycles and for DMA operations
The ESC performs cycle translation between the EISA Bus and ISA Bus For mis-matched master slave
combinations the ESC controls the data swap logic that is located in the PCEB This control is provided
through the PCEB ESC interface
DMA Controller
The ESC incorporates the functionality of two 82C37 DMA controllers with seven independently programma-
ble channels Each channel can be programmed for 8 or 16 bit DMA device size and ISA-compatible type
‘‘A’’ type ‘‘B’’ or type ‘‘C’’ timings Full 32 bit addressing is provided The DMA controller is also responsible
for generating refresh cycles
The DMA controller supports an enhanced feature called scatter gather This feature provides the capability
of transferring multiple buffers between memory and I O without CPU intervention In scatter gather mode
the DMA can read the memory address and word count from an array of buffer descriptors located in main
memory called the scatter gather descriptor (SGD) table This allows the DMA controller to sustain DMA
transfers until all of the buffers in the SGD table are handled
Interrupt Controller
The ESC contains an EISA compatible interrupt controller that incorporates the functionality of two 82C59
Interrupt Controllers The two interrupt controllers are cascaded providing 14 external and two internal inter-
rupts
16










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