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PDF ( 数据手册 , 数据表 ) 81080V

零件编号 81080V
描述 3.3V In-System Programmable SuperBIG High Density PLD
制造商 Lattice Semiconductor
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81080V 数据手册, 描述, 功能
ispLSI® 81080V
3.3V In-System Programmable
SuperBIG™ High Density PLD
Features
• SuperBIG HIGH DENSITY IN-SYSTEM
PROGRAMMABLE LOGIC
— 3.3V Power Supply
— 60,000 PLD Gates/1080 Macrocells
— 192-360 I/O Pins Supporting 3.3V/2.5V I/O
— 1440 Registers
— High-Speed Global and Big Fast Megablock (BFM)
Interconnect
— Wide 20-Macrocell Generic Logic Block (GLB) for
High Performance
— Wide Input Gating (44 Inputs per GLB) for Fast
Counters, State Machines, Address Decoders, Etc.
— PCB-Efficient Ball Grid Array (BGA) Package
Options
• HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
fmax = 125 MHz Maximum Operating Frequency
tpd = 8.5 ns Propagation Delay
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path
Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND
3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture, Symmetrical
Generic Logic Blocks Connected by Hierarchical
Big Fast Megablock and Global Routing Planes
— Product Term Sharing Array Supports up to 28
Product Terms per Macrocell Output
— Macrocells Support Concurrent Combinatorial and
Registered Functions
— Embedded Tristate Bus Can Be Used as an Internal
Tristate Bus or as an Extension of an External
Tristate Bus
— Macrocell and I/O Registers Feature Multiple Control
Options, Including Set, Reset and Clock Enable
— I/O Pins Support Programmable Bus Hold, Pull-Up,
Open-Drain and Slew Rate Options
— Separate VCCIO Power Supply to Support 3.3V or
2.5V Input/Output Logic Levels
— I/O Cell Register Programmable as Input Register for
Fast Setup Time or Output Register for Fast Clock to
Output Time
• ispDesignEXPERT™ – LOGIC COMPILER AND COM-
PLETE ISP DEVICE DESIGN SYSTEMS FROM HDL
SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING
— Superior Quality of Results
— Tightly Integrated with Leading CAE Vendor Tools
— Productivity Enhancing Timing Analyzer, Explore
Tools, Timing Simulator and ispANALYZER™
— PC and UNIX Platforms
Functional Block Diagram
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
12
I/O
Big Fast Megablock 0
12
I/O
12
I/O
Big Fast Megablock 1
12
I/O
12
I/O
Big Fast Megablock 2
12
I/O
12
I/O
Big Fast Megablock 3
12
I/O
12
I/O
Big Fast Megablock 4
Global Routing Plane
12
I/O
Big Fast Megablock 5
12
I/O
12
I/O
12
I/O
Big Fast Megablock 6
12
I/O
12
I/O
Big Fast Megablock 7
12
I/O
12
I/O
Boundary
Scan
Big Fast Megablock 8
12
I/O
12 12 12 12 12 12
I/O I/O I/O I/O I/O I/O
81080v block
ispLSI 8000V Family Description
The ispLSI 8000V Family of Register-Intensive, 3.3V
SuperBIG In-System Programmable Logic Devices is
based on Big Fast Megablocks of 120 registered macro-
cells and a Global Routing Plane (GRP) structure
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
July 2000
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
81080v_03
1







81080V pdf, 数据表
Specifications ispLSI 81080V
Output Control Organization
In addition to the data input and output to the I/O cells,
each I/O cell can have up to six different I/O cell control
signals. In addition to the internal OE control, the five
control signals for each I/O cell consist of pin OE control,
clock enable, clock input, asynchronous preset and asyn-
chronous reset. All of the I/O control signals can be driven
either from the dedicated external input pins or from the
internal control bus.
The output enable of each I/O cell can be driven by 21
different sources 16 from the output control bus, four
from the Global OE pins and one from the Test OE pin.
The Global OE signals and Test OE signal are driven
from the dedicated external control input pins.
The 16-bit wide output control buses are organized in four
different quadrants as shown in Figure 5. Since each
GLB is capable of generating the output control signals,
each of the output control bus signals can be driven from
a unique GLB. The 54 GLBs can generate a total of 54
unique I/O control signals. Referring to Figure 2, the GLB
generates its output control signal from control product
term (PT81).
Figure 5 also illustrates how the quadrant clocks are
routed to the appropriate quadrant I/O cells.
Figure 5. Output Control Bus and Quadrant Organization
Quadrant 0, 16-Bit Wide Output Control Bus
(I/O B0-B8 <0-11>, QIOCLK0)
GLB
Generated
Output
Control
(see Figure 2)
From PT81
Quadrant 2, 16-Bit Wide Output Control Bus
(I/O B0-B8 <12-23>, QIOCLK2)
8
OE Bus/80180V







81080V equivalent, schematic
Specifications ispLSI 81080V
Internal Timing Parameters
Over Recommended Operating Conditions
PARA-
METER #2
DESCRIPTION
-125
MIN MAX
BFM / Global Routing Pool Delay
tbfmi 61 BFM Routing Delay, Signal from I/O Cell
tgrpi 62 GRP Delay, Signal from I/O Cell
tgrpiz 63 Internal Tristate Bus Enable/Disable, I/O Cell Buffer
tbfmm 64 BFM Routing Delay, Signal from Macrocell
tgrpm 65 GRP Delay, Signal from Macrocell
tgrpmz 66 Internal Tristate Bus Enable/Disable, Macrocell Buffer
tbfmg 67 BFM Routing Delay, Signal from GRP
tgrpb 68 GRP Delay, Signal from BFM Routing
tbcom 69 BFM Routing to I/O Cell, Combinatorial Path
tbreg 70 BFM Routing to I/O Cell, Registered Path
tgcom 71 GRP to I/O Cell, Combinatorial Path
tgreg 72 GRP to I/O Cell, Registered Path
0.4
1.0
1.8
4.3
0.6
2.6
3.6
3.3
1.3
1.5
2.3
0.8
1.6
I/O Control Bus Delay
tpiock 73 Product Term as I/O Cell Register Clock
tpiocken 74 Product Term as I/O Cell Register Clock Enable
tpoe 75 Product Term as Output Buffer Enable/Disable
tpiorst 76 Product Term as I/O Cell Register Reset or Set Delay
tpioz 77 Internal Tristate Bus Control Signal for I/O Cell Buffer
4.1
4.6
5.6
4.3
3.3
Global Control Delay
tgck 78 Global Macrocell Register Clk
tgcken 79 Global Macrocell Register Clk Enable
tgiock 80 Global I/O Register Clk
tgiocken 81 Global I/O Register Clk Enable
tqck 82 Quadrant I/O Register Clk
tgoe 83 Global Output Enable
ttoe 84 Test Output Enable
tgmrst 85 Global GLB Register Reset
tgiorst 86 Global I/O Cell Register Reset
3.9 4.1
6.4 6.4
3.4 3.9
6.5 6.5
1.9 1.9
5.6
8.5
7.6
5.4
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
-90
MIN MAX
0.6 1.3
1.9
4.9
0.7
3.0
4.3
3.3
1.5
1.7
2.6
0.8
1.7
4.7
5.3
6.5
5.0
3.8
4.3 4.9
7.5 7.5
4.0 4.4
7.5 7.5
2.0 2.9
8.3
10.1
7.8
6.4
-60
MIN MAX UNITS
0.8 1.9 ns
2.8 ns
7.3 ns
1.1 ns
4.5 ns
6.5 ns
4.9 ns
2.3 ns
2.6 ns
4.0 ns
1.2 ns
2.6 ns
7.2 ns
8.1 ns
9.9 ns
7.6 ns
5.8 ns
6.6 7.5
11.4 11.4
6.1 6.5
11.4 11.4
3.1 4.5
12.4
15.2
11.8
9.6
ns
ns
ns
ns
ns
ns
ns
ns
ns
16










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