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PDF ( 数据手册 , 数据表 ) ML2008CP

零件编号 ML2008CP
描述 P Compatible Logarithmic Gain/Attenuator
制造商 Micro Linear
LOGO Micro Linear LOGO 


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ML2008CP 数据手册, 描述, 功能
March 1997
ML2008*, ML2009**
µP Compatible Logarithmic Gain/Attenuator
GENERAL DESCRIPTION
The ML2008 and ML2009 are digitally controlled
logarithmic gain/attenuators with a range of –24 to +24dB
in 0.1dB steps.
Easy interface to microprocessors is provided by an input
latch and control signals consisting of chip select and
write.
The interface for gain setting of the ML2008 is by an 8-bit
data word, while the ML2009 is designed to interface to a
16-bit data bus with a single write operation by hard-
wiring the gain/attenuation pin or LSB pin. The ML2008
can be power downed by the microprocessor utilizing a
bit in the second write operation.
Absolute gain accuracy is 0.05dB max over supply
tolerance of ±10% and temperature range.
These CMOS logarithmic gain/attenuators are designed for
a wide variety of applications in telecom, audio, sonar or
general purpose function generation.
FEATURES
s Low noise
0dBrnc max with +24dB gain
s Low harmonic distortion
–60dB max
s Gain range
–24 to +24dB
s Resolution
0.1dB steps
s Flat frequency response
±0.05dB from 0.3-4kHz
±0.10dB from 0.1-20kHz
s Low supply current
4mA max from ±5V supplies
s TTL/CMOS compatible digital interface
s ML2008 is designed to interface to an 8-bit data bus;
ML2009 to 16-bit data bus
* This Part Is End Of Life As Of August 1, 2000
** This Part Is Obsolete
BLOCK DIAGRAM
ML2008
ML2009*
VCC VSS GND AGND
VCC VSS GND AGND
+5
VIN
WR
CS
A0
–5
+
COARSE
RESISTORS/
SWITCHES
16
+
FINE
RESISTORS/
SWITCHES
16
+
BUFFER
VOUT
DECODERS
8
REGISTER 0
1
PDN
1
REGISTER 1
8
D1–D8
+5
VIN
WR
CS
–5
+
COARSE
+
FINE
RESISTORS/
SWITCHES
16
RESISTORS/
SWITCHES
16
DECODERS
9
REGISTER 0
9
D0–D8
+
BUFFER
VOUT
1







ML2008CP pdf, 数据表
ML2008, ML2009
D8 D7 D6 D5 D4 D3 D2 D1 BIT
A0 = 0 ATTEN/GAIN C3 C2 C1 C0 F3 F2 F1 REG 0
A0 = 1
PDN F0 REG 1
Figure 10. ML2008 Register Structure
D8 D7 D6 D5 D4 D3 D2 D1 D0 BIT
ATTEN/GAIN C3 C2 C1 C0 F3 F2 F1 F0 REG 0
Figure 11. ML2009 Register Structure
ML2008
VIN VOUT
CS WR A0 D1-D8
µP
8
Figure 12. Typical 8-Bit µP Interface, Double Write
ML2009
VIN VOUT
CS WR D1-D8 D0
+5V
µP
8
Figure 13. Typical 8-Bit µP Interface, Single Write
ML2009
CS WR D0-D8
µP
9
Figure 14. Typical 16-Bit µP Interface
8
ML2009
VIN VOUT
D0-D8 WR CS
ML2233
VIN
12-BIT
+ SIGN
A/D
µP
OR
DSP
Figure 15. AGC for DSP or Modem Front End














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