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PDF ( 数据手册 , 数据表 ) M93S66

零件编号 M93S66
描述 4Kbit / 2Kbit and 1Kbit 16-bit wide MICROWIRE Serial Access EEPROM with Block Protection
制造商 ST Microelectronics
LOGO ST Microelectronics LOGO 


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M93S66 数据手册, 描述, 功能
M93S66, M93S56
M93S46
4Kbit, 2Kbit and 1Kbit (16-bit wide)
MICROWIRE Serial Access EEPROM with Block Protection
FEATURES SUMMARY
s Industry Standard MICROWIRE Bus
s Single Supply Voltage:
– 4.5V to 5.5V for M93Sx6
– 2.5V to 5.5V for M93Sx6-W
– 1.8V to 5.5V for M93Sx6-R
s Single Organization: by Word (x16)
s Programming Instructions that work on: Word or
Entire Memory
s Self-timed Programming Cycle with Auto-Erase
s User Defined Write Protected Area
s Page Write Mode (4 words)
s Ready/Busy Signal During Programming
s Speed:
– 1MHz Clock Rate, 10ms Write Time (Current
product, identified by process identification
letter F or M)
– 2MHz Clock Rate, 5ms Write Time (New
Product, identified by process identification
letter W)
s Sequential Read Operation
s Enhanced ESD/Latch-Up Behavior
s More than 1 Million Erase/Write Cycles
s More than 40 Year Data Retention
Figure 1. Packages
8
1
PDIP8 (BN)
8
1
SO8 (MN)
150 mil width
TSSOP8 (DS)
3x3mm body size
TSSOP8 (DW)
169 mil width
May 2003
1/32







M93S66 pdf, 数据表
M93S66, M93S56, M93S46
Figure 5. PAWRITE and WRAL Sequence
PAGE
WRITE
PRE
W
S
D 1 1 1 An A0 Dn
Q
ADDR
OP
CODE
CHECK
STATUS
D0
DATA IN
BUSY
READY
WRITE
ALL
PRE
W
S
D 1 0 0 0 1 Xn X0 Dn
CHECK
STATUS
D0
Q
ADDR
OP
CODE
DATA IN
BUSY
READY
AI00890C
Note: For the meanings of An, Xn and Dn, please see Table 2 and Table 3.
Page Write
A Page Write to Memory (PAWRITE) instruction
contains the first address to be written, followed by
up to 4 data words.
After the receipt of each data word, bits A1-A0 of
the internal address register are incremented, the
high order bits remaining unchanged (A7-A2 for
M93S66, M93S56; A5-A2 for M93S46). Users
must take care, in the software, to ensure that the
last word address has the same upper order ad-
dress bits as the initial address transmitted to
avoid address roll-over.
The Page Write to Memory (PAWRITE) instruction
will not be executed if any of the 4 words address-
es the protected area.
Write Enable (W) must be held High before and
during the instruction. Input address and data, on
Serial Data Input (D) are sampled on the rising
edge of Serial Clock (C).
After the last data bit has been sampled, the Chip
Select Input (S) must be taken Low before the next
rising edge of Serial Clock (C). If Chip Select Input
(S) is brought Low before or after this specific time
frame, the self-timed programming cycle will not
8/32







M93S66 equivalent, schematic
M93S66, M93S56, M93S46
Table 8. AC Measurement Conditions (M93Sx6)
Symbol
Parameter
CL Load Capacitance
Input Rise and Fall Times
Input Pulse Voltages
Input Timing Reference Voltages
Output Timing Reference Voltages
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Min.
Max.
100
50
0.4 V to 2.4 V
1.0 V and 2.0 V
0.8 V and 2.0 V
Table 9. AC Measurement Conditions (M93Sx6-W and M93Sx6-R)
Symbol
Parameter
Min.
Max.
CL Load Capacitance
100
Input Rise and Fall Times
50
Input Pulse Voltages
0.2VCC to 0.8VCC
Input Timing Reference Voltages
0.3VCC to 0.7VCC
Output Timing Reference Voltages
0.3VCC to 0.7VCC
Note: 1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 9. AC Testing Input Output Waveforms
2.4V
0.4V
M93SXX
2V
1V
INPUT
OUTPUT
2.0V
0.8V
0.8VCC
0.2VCC
M93SXX-W & M93SXX-R
0.7VCC
0.3VCC
AI02791
Unit
pF
ns
V
V
V
Unit
pF
ns
V
V
V
Table 10. Capacitance
Symbol
Parameter
Test Condition Min Max Unit
COUT
Output
Capacitance
VOUT = 0V
5 pF
CIN Input
Capacitance
VIN = 0V
5 pF
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 1 MHz.
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