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PDF ( 数据手册 , 数据表 ) M82C288-10

零件编号 M82C288-10
描述 BUS CONTROLLER FOR M80286 PROCESSORS
制造商 Intel
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M82C288-10 数据手册, 描述, 功能
M82C288
BUS CONTROLLER FOR M80286 PROCESSORS
(M82C288-10 M82C288-8 M82C288-6)
Military
Y Provides Commands and Controls for
Local and System Bus
Y Wide Flexibility in System
Configurations
Y Implemented in High Speed CHMOS III
Technology
Y Fully Compatible with the HMOS
M82288
Y Fully Static Device
Y Single a5V Supply
Y Available in 20 Pin Cerdip Package
(See Packaging Spec Order 231369)
The Intel M82C288 Bus Controller is a 20-pin CHMOS III component for use in M80C286 microsystems The
M82C288 is fully compatible with its predecessor the HMOS M82288 The bus controller is fully static and
supports a low power mode The bus controller provides command and control outputs with flexible timing
options Separate command outputs are used for memory and I O devices The data bus is controlled with
separate data enable and direction control signals
Two modes of operation are possible via a strapping option MULTIBUS Compatible bus cycles and high
speed bus cycles
20 Pin Cerdip Package
Figure 1 M82C288 Block Diagram
271077 – 1
271077 – 2
Figure 2 M82C288 Pin
Configuration
November 1991
Order Number 271077-006







M82C288-10 pdf, 数据表
M82C288
Bus cycles can occur back to back with no TI bus
states between TC and TS Back to back cycles do
not affect the timing of the command and control
outputs Command and control outputs always
reach the states shown for the same clock edge
(within TS TC or following bus state) of a bus cycle
A special case in control timing occurs for back to
back write cycles with MB e 0 In this case DT R
and DEN remain HIGH between the bus cycles (see
Figure 8) The command and ALE output timing
does not change
Figures 9 and 10 show a MULTIBUS I cycle with MB
e 1 AEN and CMDLY are connected to GND The
effects of CMDLY and AEN are described later in
the section on control inputs Figure 9 shows a read
cycle with one wait state and Figure 10 shows a
write cycle with two waits states The second wait
state of the write cycle is shown only for example
purposes and is not required The READY input is
shown to illustate how wait states are added
271077 – 8
Figure 8 Write-Write Bus Cycles with MB e 0
Figure 9 Idle-Read-Idle Bus Cycles with 1 Wait State and with MB e 1
271077 – 9
8







M82C288-10 equivalent, schematic
M82C288
271077 – 15
Note 9 AC Test Loading on Outputs
271077 – 14
Note 8 AC Setup Hold and Delay Time
Measurement General
WAVEFORMS
CLK CHARACTERISTICS
271077 – 16
16










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