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PDF ( 数据手册 , 数据表 ) M82380

零件编号 M82380
描述 HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH INTEGRATED SYSTEM SUPPORT PERIPHERALS
制造商 Intel
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M82380 数据手册, 描述, 功能
M82380
HIGH PERFORMANCE 32-BIT DMA CONTROLLER WITH
INTEGRATED SYSTEM SUPPORT PERIPHERALS
Y High Performance 32-Bit DMA
Controller
40 Mbytes sec Maximum Data
Transfer Rate at 20 MHz
8 Independently Programmable
Channels
Y 20-Source Interrupt Controller
Individually Programmable Interrupt
Vectors
15 External 5 Internal Interrupts
M8259A Superset
Y Four 16-Bit Programmable Interval
Timers
M82C54 Compatible
Y Programmable Wait State Generator
0 to 15 Wait States Pipelined
1 to 16 Wait States Non-Pipelined
Y DRAM Refresh Controller
Y i386TM Processor Shutdown Detect and
Reset Control
Software Hardware Reset
Y High Speed CHMOS III Technology
Y 132-Pin PGA Package and 164-Pin Quad
Flat Pack
(See Packaging Specification Order 231369)
Y Optimized for use with the i386TM
Microprocessor
Resides on Local Bus for Maximum
Bus Bandwidth
Y Available in Three Product Grades
MIL-STD-883 b55 C to a125 C (TC)
Military Temperature Only
b55 C to a125 C (TC)
Extended Temperature
b40 C to a110 C (TC)
The M82380 is a multi-function support peripheral that integrates system functions necessary in an i386
processor environment It has eight channels of high performance 32-bit DMA with the most efficient transfer
rates possible on the i386 microprocessor bus System support peripherals integrated into the M82380 provide
Interrupt Control Timers Wait State generation DRAM Refresh Control and System Reset logic
The M82380’s DMA Controller can transfer data between devices of different data path widths using a single
channel Each DMA channel operates independently in any of several modes Each channel has a temporary
data storage register for handling non-aligned data without the need for external alignment logic
November 1992
M82380 Internal Block Diagram
271070 – 1
Order Number 271070-006







M82380 pdf, 数据表
M82380
The M82380 DMA controller transfers blocks of data
(buffers) in three modes Single Buffer Buffer Auto-
Initialize and Buffer Chaining In the Single Buffer
Process the M82380 DMA Controller is pro-
grammed to transfer one particular block of data
Successive transfers then require reprogramming of
the DMA channel Single Buffer transfers are useful
in systems where it is known at the time the transfer
begins what quantity of data is to be transferred and
there is a contiguous block of data area available
The Buffer Auto-Initialize Process allows the same
data area to be used for successive DMA transfers
without having to reprogram the channel
The Buffer Chaining Process allows a program to
specify a list of buffer transfers to be executed The
M82380 DMA Controller through interrupt routines
is reprogrammed from the list The channel is repro-
grammed for a new buffer before the current buffer
transfer is complete This pipelining of the channel
programming process allows the system to allocate
non-contiguous blocks of data storage space and
transfer all of the data with one DMA process The
buffers that make up the chain do not have to be in
contiguous locations
Channel priority can be fixed or rotating Fixed priori-
ty allows the programmer to define the priority of
DMA channels based on hardware or other fixed pa-
rameters Rotating priority is used to provide periph-
erals access to the bus on a shared basis
With fixed priority the programmer can set any
channel to have the current lowest priority This al-
lows the user to reset or manually rotate the priority
schedule without reprogramming the command reg-
isters
1 1 2 PROGRAMMABLE INTERVAL TIMERS
Four 16-bit programmable interval timers reside
within the M82380 These timers are identical in
function to the timers in the M82C54 Programmable
Interval Timer All four of the timers share a common
clock input which can be independent of the system
clock The timers are capable of operating in six dif-
ferent modes In all of the modes the current count
can be latched and read by the i386 processor at
any time making these very versatile event timers
Figure 3 shows the functional components of the
Programmable Interval Timers
The outputs of the timers are directed to key system
functions making system design simpler Timer 0 is
routed directly to an interrupt input and is not avail-
able externally This timer would typically be used to
generate time-keeping interrupts
Timers 1 and 2 have outputs which are available for
general timer counter purposes as well as special
functions Timer 1 is routed to the refresh control
logic to provide refresh timing Timer 2 is connected
to an interrupt request input to provide other timer
functions Timer 3 is a general purpose timer coun-
ter whose output is available to external hardware It
is also connected internally to the interrupt request
which defaults to the highest priority (IRQ0)
Figure 3 Programmable Interval Timers Block Diagram
271070 – 4
8







M82380 equivalent, schematic
M82380
Table 3 Output Signals Following RESET
Signal
Level
A2– A31 D0–D31 BE0 –BE3
D C W R M IO ADS
READYO
EOP
EDACK2 – EDACK0
HOLD
INT
TOUT1 REF TOUT2 IRQ3 TOUT3
CPURST
Float
Float
‘1’
‘1’ (Weak Pull-UP)
‘100’
‘0’
UNDEFINED
UNDEFINED
‘0’
The Interrupt Controller and Programmable Interval Timer are initialized by software commands
processor The M82380 is reset by asserting RESET
for 15 or more CLK2 periods When RESET is as-
serted all other input pins are ignored and all other
bus pins are driven to an idle bus state as shown in
Table 3 The M82380 will determine the phase of its
internal clock following RESET going inactive
RESET is level-sensitive and must be synchronous
to the CLK2 signal Therefore this RESET input
should be tied to the RESET output of the Clock
Generator The RESET setup and hold time require-
ments are shown in Figure 8
CPURST
This output signal is used to reset the i386 host
processor It will go active (HIGH) whenever one of
the following events occurs a) M82380’s RESET in-
put is active b) a software RESET command is is-
sued to the M82380 or c) when the M82380 detects
a processor Shutdown cycle and when this detec-
tion feature is enabled (see CPU Reset and Shut-
down Detect) When activated CPURST will be held
active for 62 CLK2 periods The timing of CPURST is
such that the i386 processor will be in synchroniza-
tion with the M82380 This timing is shown in
Figure 9
T30-RESET Hold Time
T31-RESET Setup Time
Figure 8 RESET Timing
271070 – 9
T33-CPU Reset from CLK2
Figure 9 CPURST Timing
16
271070 – 10










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