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PDF ( 数据手册 , 数据表 ) M74HCT126

零件编号 M74HCT126
描述 QUAD BUS BUFFERS 3-STATE
制造商 ST Microelectronics
LOGO ST Microelectronics LOGO 


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M74HCT126 数据手册, 描述, 功能
M54/74HCT125
M54/74HCT126
QUAD BUS BUFFERS (3-STATE)
. HIGH SPEED
tPD = 12 ns (TYP.) AT VCC = 5 V
. LOW POWER DISSIPATION
ICC = 4 µA (MAX.) AT 25 °C
. OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
. BALANCED PROPAGATION DELAYS
tPLH = tPHL
. SYMMETRICAL OUTPUT IMPEDANCE
IOL = IOH= 6 mA (MIN.)
. COMPATIBLE WITH TTL OUTPUTS
VIH = 2V (MIN.) VIL = 0.8V (MAX)
. PIN AND FUNCTION COMPATIBLE
WITH 54/74LS125/126
B1R
(Plastic Package)
F1R
(Ceramic Package)
M 1R
(Micro Package)
C1R
(Chip Carrier)
DESCRIPTION
The M54/74HCT125/126 are high speed CMOS
QUAD BUS BUFFER (3-STATE) FABRICATED IN
SILICON GATE C2MOS technology. They have the
same high speed performance of LSTTL combined
with true CMOS low power consumption. These de-
vices require the same 3-STATE control input G to
be taken high to make the output go into the high im-
pedance state.This integrated circuit has input and
output characteristics that are fully compatible with
54/74 LSTTL logic families. M54/74HCT devices
are designed to directly interface HSC2MOS sys-
tems with TTL and NMOS components. They are
also plug in replacements for LSTTL devices giving
a reduction of power consumption. All inputs are
equipped with protection circuits against static dis-
charge and transient excess voltage.
ORDER CODES :
M54HCTXXXF1R M74HCTXXXM1R
M74HCTXXXB1R M74HCTXXXC1R
PIN CONNECTIONS (top view)
HCT125
INPUT AND OUTPUT EQUIVALENT CIRCUIT
HCT126
October 1993
NC =
No Internal
Connection
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M74HCT126 pdf, 数据表
M54/M74HCT125/126
DIM.
A
a1
a2
b
b1
C
c1
D
E
e
e3
F
G
L
M
S
MIN.
0.1
0.35
0.19
8.55
5.8
3.8
4.6
0.5
SO14 MECHANICAL DATA
mm
TYP.
0.5
1.27
7.62
MAX.
1.75
0.2
1.65
0.46
0.25
MIN.
0.003
0.013
0.007
45° (typ.)
8.75 0.336
6.2 0.228
4.0 0.149
5.3 0.181
1.27 0.019
0.68
8° (max.)
inch
TYP.
0.019
0.050
0.300
MAX.
0.068
0.007
0.064
0.018
0.010
0.344
0.244
0.157
0.208
0.050
0.026
P013G
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