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PDF ( 数据手册 , 数据表 ) M7232

零件编号 M7232
描述 Numeric/Alphanumeric Triplexed LCD Display Drivers
制造商 Intersil
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M7232 数据手册, 描述, 功能
ICM7231, ICM7232
August 1997
Numeric/Alphanumeric Triplexed
LCD Display Drivers
Features
Description
• ICM7231 Drives 8 Digits of 7 Segments with Two
Independent Annunciators Per Digit Address and Data
Input in Parallel Format
• ICM7232 Drives 10 Digits of 7 Segments with Two
Independent Annunciators Per Digit Address and Data
Input in Serial Format
• All Signals Required to Drive Rows and Columns of
Triplexed LCD Display are Provided
• Display Voltage Independent of Power Supply
• On-Chip Oscillator Provides All Display Timing
The ICM7231 and ICM7232 family of integrated circuits are
designed to generate the voltage levels and switching wave-
forms required to drive triplexed liquid-crystal displays.
These chips also include input buffer and digit address
decoding circuitry allowing six bits of input data to be
decoded into 64 independent combinations of the output
segments of the selected digit.
The family is designed to interface to modern high-
performance microprocessors and microcomputers and
ease system requirements for ROM space and CPU time
needed to service a display.
• Total Power Consumption Typically 200µW, Maximum
500µW at 5V
• Low-Power Shutdown Mode Retains Data With 5µW
Typical Power Consumption at 5V, 1µW at 2V
• Direct Interface to High-Speed Microprocessors
Ordering Information
PART NUMBER
TEMP. RANGE (oC)
PACKAGE
ICM7231BFIJL
-25 to 85
40 Ld CERDIP
ICM7231BFIPL
-25 to 85
40 Ld PDIP
ICM7232BFIPL
-25 to 85
40 Ld PDIP
ICM7232CRIPL
-25 to 85
40 Ld PDIP
NOTE:
All versions intended for triplexed LCD displays.
NUMBER OF DIGITS
8 Digit
8 Digit
10 Digit
10 Digit
INPUT FORMAT
Parallel
Parallel
Serial
Serial
PKG. NO.
F40.6
E40.6
E40.6
E40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
9-19
File Number 3161.1







M7232 pdf, 数据表
ICM7231, ICM7232
Timing Diagrams
AN1
AN2
BD0
BD1
BD2
BD3
A0
A1
A2
A3
ENTER
ENTER
FIRST
LAST
ICM7232 WRITE ORDER
DATA
CLOCK
INPUT
DATA
INPUT
tCI
tDS
1
BD0
DATA
VALID
tCI
2
tDH
BD1
DATA
VALID
3
BD2
DATA
VALID
7
A2
DATA
VALID
8
A3
DATA
VALID
DATA
ACCEPTED
OUTPUT
tWLL
WRITE
INPUT
tWP
tODI
tCWS
tODH
tWP
RESETS SHIFT REGISTER
AND INPUT CONTROL
LOGIC WHEN DATA
ACCEPTED HIGH
DO NOT CARE
DECODES AND STORES
DATA, RESETS SHIFT
REGISTER AND LOGIC
WHEN DATA ACCEPTED
IS LOW
FIGURE 3. ICM7232 INPUT TIMING DIAGRAM, LEAVING BOTH ANNUNCIATORS OFF
ICM7231 Family Description
The ICM7231 drives displays with 8 seven-segment digits with
two independent annunciators per digit, accepting six data
bits and three digit address bits from parallel inputs controlled
by a chip select input. The data bits are subdivided into four
binary code bits and two annunciator control bits.
The ICM7232 drives 10 seven-segment digits with two inde-
pendent annunciators per digit. To write into the display, six
bits of data and four bits of digit address are clocked serially
into a shift register, then decoded and written to the display.
Input levels are TTL compatible, and the DATA ACCEPTED
output on the serial input devices will drive one LSTTL load.
The intermediate voltage levels necessary to drive the dis-
play properly are generated by an on-chip resistor string,
and the output of a totally self-contained on-chip oscillator is
used to generate all display timing. All devices in this family
have been fabricated using Intersil’ MAXCMOS® process
and all inputs are protected against static discharge.
Triplexed (1/3 Multiplexed) Liquid Crystal Displays
Figure 4 shows the connection diagram for a typical
7-segment display with two annunciators such as would be
used with an ICM7231 or ICM7232 numeric display driver.
Figure 5 shows the voltage waveforms of the common lines
and one segment line, chosen for this example to be the “a,
g, d” segment line. This line intersects with BP1 to form the
“a” segment, BP2 to form the “g” segment and BP3 to form
the “d” segment. Figure 5 also shows the waveform of the “a,
g, d” segment line for four different ON/OFF combinations of
the “a”, “g” and “d” segments. Each intersection (segment or
annunciator) acts as a capacitance from segment line to
common line, shown schematically in Figure 6. Figure 7
shows the voltage across the “g” segment for the same four
combinations of ON/OFF segments used in Figure 5.
SEGMENT LINES
BP1
a
fb
g
BP2
ec
d BP3
an2 an1
SEGMENT LINE CONNECTIONS
a
fb
g
ec
an2 d an1
BACKPLANE CONNECTIONS
FIGURE 4. CONNECTION DIAGRAMS FOR TYPICAL
7-SEGMENT DISPLAYS
MAXCMOS® is a registered trademark of Intersil Corporation.
9-26







M7232 equivalent, schematic
ICM7231, ICM7232
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
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