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PDF ( 数据手册 , 数据表 ) 7812

零件编号 7812
描述 +2.7 V to +5.5 V/ 350 kSPS/ 10-Bit 4-/8-Channel Sampling ADCs
制造商 Analog Devices
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7812 数据手册, 描述, 功能
a
2.7 V to 5.5 V, 350 kSPS, 10-Bit
4-/8-Channel Sampling ADCs
AD7811/AD7812
FEATURES
10-Bit ADC with 2.3 s Conversion Time
The AD7811 has Four Single-Ended Inputs that
Can Be Configured as Three Pseudo Differential
Inputs with Respect to a Common, or as Two Inde-
pendent Pseudo Differential Channels
The AD7812 has Eight Single-Ended Inputs that Can
Be Configured as Seven Pseudo Differential Inputs
with Respect to a Common, or as Four Independent
Pseudo Differential Channels
Onboard Track and Hold
Onboard Reference 2.5 V ؎ 2.5%
Operating Supply Range: 2.7 V to 5.5 V
Specifications at 2.7 V–3.6 V and 5 V ؎ 10%
DSP-/Microcontroller-Compatible Serial Interface
High Speed Sampling and Automatic Power-Down Modes
Package Address Pin on the AD7811 and AD7812 Allows
Sharing of the Serial Bus in Multipackage Applications
Input Signal Range: 0 V to VREF
Reference Input Range: 1.2 V to VDD
GENERAL DESCRIPTION
The AD7811 and AD7812 are high speed, low power, 10-bit
A/D converters that operate from a single 2.7 V to 5.5 V supply.
The devices contain a 2.3 µs successive approximation A/D
converter, an on-chip track/hold amplifier, a 2.5 V on-chip refer-
ence and a high speed serial interface that is compatible with the
serial interfaces of most DSPs (Digital Signal Processors) and
microcontrollers. The user also has the option of using an exter-
nal reference by connecting it to the VREF pin and setting the
EXTREF bit in the control register. The VREF pin may be tied
to VDD. At slower throughput rates the power-down mode may
be used to automatically power down between conversions.
The control registers of the AD7811 and AD7812 allow the
input channels to be configured as single-ended or pseudo
differential. The control register also features a software convert
start and a software power-down. Two of these devices can
share the same serial bus and may be individually addressed in
a multipackage application by hardwiring the device address pin.
The AD7811 is available in a small, 16-lead 0.3" wide, plastic
dual-in-line package (mini-DIP), in a 16-lead 0.15" wide, Small
Outline IC (SOIC) and in a 16-lead, Thin Shrink Small Out-
line Package (TSSOP). The AD7812 is available in a small,
20-lead 0.3" wide, plastic dual-in-line package (mini-DIP), in a
20-lead, Small Outline IC (SOIC) and in a 20-lead, Thin Shrink
Small Outline Package (TSSOP).
PRODUCT HIGHLIGHTS
1. Low Power, Single Supply Operation
Both the AD7811 and AD7812 operate from a single 2.7 V
to 5.5 V supply and typically consume only 10 mW of power.
The power dissipation can be significantly reduced at
lower throughput rates by using the automatic power-
down mode e.g., 315 µW @ 10 kSPS, VDD = 3 V—see
Power vs. Throughput.
2. 4-/8-Channel, 10-Bit ADC
The AD7811 and AD7812 have four and eight single-ended
input channels respectively. These inputs can be configured
as pseudo differential inputs by using the Control Register.
3. On-chip 2.5 V (± 2.5%) reference circuit that is powered
down when using an external reference.
4. Hardware and Software Control
The AD7811 and AD7812 provide for both hardware and
software control of Convert Start and Power-Down.
CREF
VIN1
VIN2
VIN3
VIN4
MUX
FUNCTIONAL BLOCK DIAGRAMS
REFIN
VDD AGND DGND
CREF
1.23V
REF
BUF
CLOCK
OSC
CHARGE
REDISTRIBUTION
DAC
AD7811
SERIAL
PORT
VDD /3
COMP
CONTROL
LOGIC
DOUT
DIN
RFS
TFS
SCLK
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
MUX
REFIN
VDD AGND DGND
1.23V
REF
BUF
CLOCK
OSC
CHARGE
REDISTRIBUTION
DAC
AD7812
SERIAL
PORT
DOUT
DIN
RFS
TFS
SCLK
VDD /3
COMP
CONTROL
LOGIC
A0 CONVST
A0 CONVST
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000







7812 pdf, 数据表
AD7811/AD7812
Control Register (AD7812)
The Control Register is a 10-bit-wide, write only register. The Control Register is written to when the AD7812 receives a falling
edge on its TFS pin. The AD7812 will maintain the same configuration until a new control byte is written to the part. The control
register can be written to at the same time data is being read. This latter feature enhances throughput rates when software control is
being used or when the analog input channels are being changed frequently. The power-up default register contents are all zeros;
therefore, when the supplies are connected, the AD7812 is powered down by default.
Control Register AD7812
9
A0
PD1
PD0 VIN8/AGND
DIFF/SGL
CH2
CH1
0
CH0 CONVST EXTREF
A0
PD1, PD0
This is the package address bit. It is used in conjunction with the package address pin to allow two AD7812s to
share the same serial bus. The AD7812 can also share the same serial bus with the AD7811. When a control word
is written to the control register of the AD7812 the control word is ignored if the package address bit in the con-
trol byte does not match how the package address pin is hardwired. Only the serial port of the device which
received the last valid control byte, i.e., the address bit matched the address pin, will attempt to drive the serial bus
on the next serial read. When the part powers up this bit is set to 0.
These bits allow the AD7812 to be fully powered down and powered up. Bit combinations PD1 = PD0 = 0 and
PD1 = PD0 = 1 override the automatic power-down decision at the end of conversion. These bits also decide the
power-down mode when the AD7812 enters a power-down at the end of a conversion. There are two power-down
modes—Full Power-Down and Partial Power-Down. See Power-Down section of this data sheet.
PD1
0
0
1
1
PD0
0
1
0
1
Description
Full Power-Down of the AD7812
Partial Power-Down at the End of Conversion
Full Power-Down at the End of Conversion
Power-Up the AD7812
VIN8/AGND
The DIF/SGL bit in the control register must be set to 0 in order to use this option otherwise this bit is ignored.
Setting VIN8/AGND to 0 configures the analog inputs of the AD7812 as eight single-ended analog inputs
referenced to analog ground (AGND). By setting this bit to 1 the input channels VIN1 to VIN7 are configured
as seven pseudo differential channels with respect to VIN8—see Table II.
DIF/SGL
This bit is used to configure the analog inputs as single ended or pseudo differential pairs. By setting this bit to 0
the analog inputs can be configured as single ended with respect to AGND, or pseudo differential with respect to
VIN8 as explained above. Setting this bit to 1 configures the analog input channels as four pseudo differential pairs
VIN1/VIN2, VIN3/VIN4, VIN5/VIN6 and VIN7/VIN8—see Table II.
CH2, CH1, CH0 These bits are used in conjunction with VIN8/AGND and DIF/SGL to select an analog input channel. Table II
shows how the various channel selections are made.
CONVST
Setting this bit to a logic one initiates a conversion. A conversion is initiated 400 ns after a write to the control
register has taken place. This allows a signal to be acquired even if the channel is changed and a conversion initi-
ated in the same write operation. The bit is reset after the end of a conversion.
EXTREF
This bit must be set to a logic one if the user wishes to use an external reference or use VDD as the reference.
When the external reference is selected the on-chip reference circuitry powers down and the current consumption
is reduced by about 1 mA.
–8– REV. B







7812 equivalent, schematic
AD7811/AD7812
RFS. The first rising SCLK edge after the rising edge of the
RFS signal causes DOUT to leave its high impedance state and
data is clocked out onto the DOUT line and also on subsequent
SCLK rising edges. The DOUT pin goes back into a high
impedance state on the 11th SCLK rising edge—Point “A” on
Figure 18. A minimum of 11 SCLKs are therefore needed to
carry out a serial read. Data on the DIN line is latched in on
the first SCLK falling edge after the falling edge of the TFS
signal and on subsequent SCLK falling edges. The control
register is updated on the 13th SCLK rising edge—point “B” on
Figure 18. A minimum of 13 SCLK pulses are therefore needed
to complete a serial write operation. In multipackage applications
the RFS and TFS signals can be used as chip select signals. The
serial interface will not shift data in or out until it receives the
active edge of the RFS or TFS signal.
Simplifying the Serial Interface
The five-wire interface is designed to support many different
serial interface standards. However, it is possible to reduce the
number of lines required to just three. By simply connecting the
TFS and RFS pins to the CONVST signal (see Figure 4), the
CONVST signal can be used to enable the serial port for read-
ing and writing. This is only possible where a noncontinuous
serial clock is being used.
MICROPROCESSOR INTERFACING
The serial interface on the AD7811 and AD7812 allows the
parts to be directly connected to a range of many different
microprocessors. This section explains how to interface the
AD7811 and AD7812 with some of the more common micro-
controller and DSP serial interface protocols.
AD7811/AD7812 to PIC16C6x/7x
The PIC16C6x Synchronous Serial Port (SSP) is configured as
an SPI Master with the Clock Polarity bit = 0. This is done
by writing to the Synchronous Serial Port Control Register
(SSPCON). See user PIC16/17 Microcontroller User Manual.
Figure 19 shows the hardware connections needed to interface
to the PIC16/17. In this example I/O port RA1 is being used to
pulse CONVST and enable the serial port of the AD7811/
AD7812. This microcontroller transfers only eight bits of data
during each serial transfer operation; therefore, two consecutive
read/write operations are needed.
AD7811/AD7812*
SCLK
DOUT
DIN
PIC16C6x/7x*
SCK/RC3
SDO/RC5
SDI/ RC4
AD7811/AD7812 to MC68HC11
The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 0), Clock Polarity Bit
(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 user manual. A connection diagram is shown in
Figure 20.
AD7811/AD7812*
SCLK
DOUT
DIN
MC68HC11*
SCLK/PD4
MISO/PD2
MOSI/PD3
CONVST
RFS
TFS
PA0
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing to the MC68HC11
AD7811/AD7812 to 8051
The AD7811/AD7812 requires a clock synchronized to the
serial data. The 8051 serial interface must therefore be operated
in Mode 0. In this mode serial data enters and exits through
RxD and a shift clock is output on TxD (half duplex). Figure 21
shows how the 8051 is connected to the AD7811/AD7812.
However, because the AD7811/AD7812 shifts data out on the
rising edge of the shift clock and latches data in on the falling
edge, the shift clock must be inverted.
AD7811/AD7812*
SCLK
DOUT
DIN
RFS
TFS
8051*
TxD
RxD
P1.1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. Interfacing to the 8051 Serial Port
CONVST
RFS
TFS
RA1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. Interfacing to the PIC16/17
–16–
REV. B










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