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PDF ( 数据手册 , 数据表 ) 74VHCT373AMTC

零件编号 74VHCT373AMTC
描述 Octal D-Type Latch with 3-STATE Outputs
制造商 Fairchild Semiconductor
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74VHCT373AMTC 数据手册, 描述, 功能
July 1997
Revised April 1999
74VHCT373A
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHCT373A is an advanced high speed CMOS octal D-
type latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a latch enable input (LE) and an out-
put enable input (OE). The latches appear transparent to
data when latch enable (LE) is HIGH. When LE is LOW, the
data that meets the setup time is latched. When the OE
input is HIGH, the eight outputs are in a high impedance
state.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1: Outputs in OFF-State.
Features
s High speed: tPD = 7.7 ns (typ) at TA = 25°C
s High Noise Immunity: VIH = 2.0V, VIL = 0.8V
s Power Down Protection is provided on all inputs and
outputs
s Low Power Dissipation:
ICC = 4 µA (max) @ TA = 25°C
s Pin and Function Compatible with 74HCT373
Ordering Code:
Order Number Package Number
Package Description
74VHCT373AM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74VHCT373ASJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHCT373AMTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHCT373AN
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
D0–D7
LE
OE
O0–O7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Outputs
© 1999 Fairchild Semiconductor Corporation DS500027.prf
www.fairchildsemi.com












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