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PDF ( 数据手册 , 数据表 ) 74VHC02

零件编号 74VHC02
描述 Quad 2-Input NOR Gate
制造商 Fairchild Semiconductor
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74VHC02 数据手册, 描述, 功能
December 2007
74VHC02
Quad 2-Input NOR Gate
Features
High Speed: tPD = 3.6ns (Typ.) at VCC = 5V
Low power dissipation: ICC = 2µA (Max.) at TA = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (Min.)
Power down protection is provided on all inputs
Low noise: VOLP = 0.8V (Max.)
Pin and function compatible with 74HC02
General Description
The VHC02 is an advanced high-speed CMOS 2-Input
NOR Gate fabricated with silicon gate CMOS technol-
ogy. It achieves the high-speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation. The internal circuit is
composed of 3 stages, including buffer output, which
provide high noise immunity and stable output. An input
protection circuit insures that 0V to 7V can be applied to
the input pins without regard to the supply voltage. This
device can be used to interface 5V to 3V systems and
two supply systems such as battery backup. This circuit
prevents device destruction due to mismatched supply
and input voltages.
Ordering Information
Order Number
Package
Number
Package Description
74VHC02M
74VHC02SJ
74VHC02MTC
M14A
M14D
MTC14
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
©1992 Fairchild Semiconductor Corporation
74VHC02 Rev. 1.4.0
www.fairchildsemi.com







74VHC02 pdf, 数据表
Physical Dimensions (Continued)
0.43 TYP
0.65
1.65
0.45
6.10
R0.09 min
12.00°TOP & BOTTOM
A. CONFORMS TO JEDEC REGISTRATION MO-153,
VARIATION AB, REF NOTE 6
B. DIMENSIONS ARE IN MILLIMETERS
1.00
C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,
AND TIE BAR EXTRUSIONS
D. DIMENSIONING AND TOLERANCES PER ANSI
Y14.5M, 1982
E. LANDPATTERN STANDARD: SOP65P640X110-14M
F. DRAWING FILE NAME: MTC14REV6
R0.09min
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
©1992 Fairchild Semiconductor Corporation
74VHC02 Rev. 1.4.0
8
www.fairchildsemi.com














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