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PDF ( 数据手册 , 数据表 ) 74VCX32244

零件编号 74VCX32244
描述 Low Voltage 32-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
制造商 Fairchild Semiconductor
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74VCX32244 数据手册, 描述, 功能
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September 2000
Revised November 2002
74VCX32244
Low Voltage 32-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX32244 contains thirty-two non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for 8-bit, 16-bit or full 32-bit operation.
The 74VCX32244 is designed for low voltage (1.2V to
3.6V) VCC applications with I/O capability up to 3.6V.
The 74VCX32244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.2V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD
2.5 ns max for 3.0V to 3.6V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
s Packages in plastic Fine-Pitch Ball Grid Array (FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX32244G
(Note 2)(Note 3)
BGA96A
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
Note 2: Ordering code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
© 2002 Fairchild Semiconductor Corporation DS500416
www.fairchildsemi.com







74VCX32244 pdf, 数据表
AC Loading and Waveforms (VCC 1.5 ± 0.1V to 1.2V)
TEST
SWITCH
tPLH, tPHL
Open
tPZL, tPLZ
VCC x 2 at VCC = 1.5 ± 0.1V
tPZH, tPHZ
GND
FIGURE 5. AC Test Circuit
FIGURE 6. Waveform for Inverting and Non-Inverting Functions
FIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage Logic
FIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
Symbol
Vmi
Vmo
VX
VY
VCC
1.5V ± 0.1V
VCC/2
VCC/2
VOL +0.1V
VOH 0.1V
www.fairchildsemi.com
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