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PDF ( 数据手册 , 数据表 ) 74VCX16821

零件编号 74VCX16821
描述 Low Voltage 20-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
制造商 Fairchild Semiconductor
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74VCX16821 数据手册, 描述, 功能
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March 1998
Revised October 2004
74VCX16821
Low Voltage 20-Bit D-Type Flip-Flops
with 3.6V Tolerant Inputs and Outputs
General Description
The VCX16821 contains twenty non-inverting D-type flip-
flops with 3-STATE outputs and is intended for bus oriented
applications.
The 74VCX16821 is designed for low voltage (1.4V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74VCX16821 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.4V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s tPD
3.5 ns max for 3.0V to 3.6V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±24 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Descriptions
74VCX16821MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
CLKn
D0D19
O0O19
Output Enable Input (Active LOW)
Clock Input
Inputs
Outputs
© 2004 Fairchild Semiconductor Corporation DS500130
www.fairchildsemi.com







74VCX16821 pdf, 数据表
AC Loading and Waveforms (VCC 1.5V ± 0.1V)
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
SWITCH
Open
VCC x 2 at VCC = 1.5V ± 0.1V
GND
FIGURE 7. AC Test Circuit
FIGURE 8. Waveform for Inverting and
Non-Inverting Functions
FIGURE 9. 3-STATE Output High Enable and
Disable Times for Low Voltage Logic
FIGURE 10. 3-STATE Output Low Enable and Disable Times for Low Voltage Logic
Symbol
Vmi
Vmo
VX
VY
VCC
1.5V ± 0.1V
VCC/2
VCC/2
VOL + 0.1V
VOH 0.1V
www.fairchildsemi.com
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