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PDF ( 数据手册 , 数据表 ) 74V1T126C

零件编号 74V1T126C
描述 SINGLE BUS BUFFER 3-STATE
制造商 STMicroelectronics
LOGO STMicroelectronics LOGO 


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74V1T126C 数据手册, 描述, 功能
® 74V1T126
SINGLE BUS BUFFER (3-STATE)
s HIGH SPEED: tPD = 3.8 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 1 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUT
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V1T126 is an advanced high-speed
CMOS SINGLE BUS BUFFER fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
PRELIMINARY DATA
S
(SOT23-5L)
C
(SC-70)
ORDER CODE:
74V1T126S
74V1T126C
3-STATE control input G has to be set LOW to
place the output into the high impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
PIN CONNECTION AND IEC LOGIC SYMBOLS
October 1999
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74V1T126C pdf, 数据表
74V1T126
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
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