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PDF ( 数据手册 , 数据表 ) 74LVQ373QSC

零件编号 74LVQ373QSC
描述 Low Voltage Octal Transparent Latch with 3-STATE Outputs
制造商 Fairchild Semiconductor
LOGO Fairchild Semiconductor LOGO 


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74LVQ373QSC 数据手册, 描述, 功能
May 1998
74LVQ373
Low Voltage Octal Transparent Latch with 3-STATE
Outputs
General Description
The LVQ373 consists of eight latches with 3-STATE outputs
for bus organized system applications. The latches appear
transparent to the data when Latch Enable (LE) is HIGH.
When LE is low, the data satisfying the input timing require-
ments is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the bus output is in
the high impedance state.
Features
n Ideal for low power/low noise 3.3V applications
n Implements patented EMI reduction circuitry
n Available in SOIC JEDEC, SOIC EIAJ and QSOP
packages
n Guaranteed simultaneous switching noise level and
dynamic threshold performance
n Improved latch-up immunity
n Guaranteed incident wave switching into 75
n 4 kV minimum ESD immunity
Ordering Code:
Order Number
74LVQ373SC
74LVQ373SJ
74LVQ373QSC
Package Number
M20B
M20D
MQA20
Package Description
20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC
20-Lead Molded Shrink Small Outline Package, SOIC EIAJ
20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SSOP JEDEC
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Assignment for
SOIC and QSOP
DS011359-1
IEEE/IEC
DS011359-2
DS011359-3
Pin Descriptions
Pin
Names
D0– D7
LE
OE
O0– O7
Description
Data Inputs
Latch Enable Input
Output Enable Input
3-STATE Latch Outputs
© 1998 Fairchild Semiconductor Corporation DS011359
www.fairchildsemi.com












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