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PDF ( 数据手册 , 数据表 ) MG115P

零件编号 MG115P
描述 0.25m Sea of Gates and Customer Structured Arrays
制造商 OKI electronic componets
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MG115P 数据手册, 描述, 功能
DATA SHEET
OKI
ASIC
PRODUCTS
MG113P/114P/115P/73P/74P/75P
0.25µm Sea of Gates and
Customer Structured Arrays
November 1999







MG115P pdf, 数据表
s MG113P/114P/115P/73P/74P/75P s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (VSS = 0 V, TJ = 25°C) [1]
Parameter
Symbol
Rated Value
Unit
Power supply voltage
Input voltage (Input Buffer)
Output voltage (Output Buffer)
Input current (Input Buffer)
Output current per I/O (Output Buffer)
Storage temperature
VDD Core (2.5 V)
VDD I/O (3.3 V)
VI
VO
II
IO
TSTG
-0.3 to +3.6
-0.3 to +4.6
-0.3 to VDD +0.3
-0.3 to VDD +0.3
-10 to +10
-24 to +24
-65 to +150
V
mA
°C
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions (VSS = 0 V)
Parameter
Symbol
Power supply voltage
Junction temperature
VDD Core (2.5 V)
VDD I/O (3.3 V)
Tj
Rated Value
+2.25 to +2.75
+3.0 to +3.6
-40 to +85
Unit
V
°C
6 Oki Semiconductor







MG115P equivalent, schematic
s MG113P/114P/115P/73P/74P/75P s ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
Design Process
The following figure illustrates the overall IC design process, also indicating the three main interface
points between external design houses and Oki ASIC Application Engineering.
VHDL/HDL Description
Synthesis
Floorplanning
Gate-Level Simulation
Netlist Conversion
(EDIF 200)
Scan Insertion (Optional)
CDC [1]
Floorplanning
Pre-Layout Simulation
(Cadence Verilog)
Layout
Verification
(Cadence DRACULA)
Post-Layout Simulation
(Cadence Verilog)
Fault Simulation [6]
Manufacturing
Prototype
Test Program
Conversion
Test Vectors
LSF[2]
Level 1 [5]
CAE Front-End
Level 2
Test Vector Conversion
(Oki TPL [4])
TDC [3]
Level 2.5 [5]
Automatic Test
Pattern Generation
(Synopsys Test Compiler)
Oki Interface
Level 3 [5]
[1] Oki’s Circuit Data Check program (CDC) verifies logic design rules
[2] Oki’s Link to Synthesis Floorplanning toolset (LSF) transfers post-floorplanning timing for resynthesis
[3] Oki’s Test Data Check program (TDC) verifies test vector rules
[4] Oki’s Test Pattern Language (TPL)
[5] Alternate Customer-Oki design interfaces available in addition to standard level 2
[6] Standard design process includes fault simulation
Figure 12. Oki’s Design Process
14 Oki Semiconductor










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