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PDF ( 数据手册 , 数据表 ) M40Z300MQ1TR

零件编号 M40Z300MQ1TR
描述 NVRAM CONTROLLER for up to EIGHT LPSRAM
制造商 ST Microelectronics
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M40Z300MQ1TR 数据手册, 描述, 功能
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M40Z300
M40Z300W
5V or 3V NVRAM Supervisor for Up to 8 LPSRAMs
FEATURES SUMMARY
CONVERTS LOW POWER SRAM INTO
NVRAMs
PRECISION POWER MONITORING AND
POWER SWITCHING CIRCUITRY
AUTOMATIC WRITE-PROTECTION WHEN
VCC IS OUT-OF-TOLERANCE
TWO-INPUT DECODER ALLOWS
CONTROL FOR UP TO 8 SRAMs (with 2
devices active in parallel)
CHOICE OF SUPPLY VOLTAGES AND
POWER-FAIL DESELECT VOLTAGES:
– M40Z300:
VCC = 4.5V to 5.5V
THS = VSS: 4.5V VPFD 4.75V
THS = VOUT: 4.2V VPFD 4.5V
– M40Z300W:
VCC = 3.0V to 3.6V
THS = VSS: 2.8V VPFD 3.0V
VCC = 2.7V to 3.3V
THS = VOUT: 2.5 VPFD 2.7V
RESET OUTPUT (RST) FOR POWER ON
RESET
BATTERY LOW PIN (BL)
LESS THAN 12ns CHIP ENABLE ACCESS
PROPAGATION DELAY (for 5.0V device)
PACKAGING INCLUDES A 28-LEAD SOIC
AND SNAPHAT® TOP (to be ordered
separately), OR A 16-LEAD SOIC
SOIC PACKAGE PROVIDES DIRECT
CONNECTION FOR A SNAPHAT TOP
WHICH CONTAINS THE BATTERY
Figure 1. 16-pin SOIC Package
16
1
SO16 (MQ)
Figure 2. 28-pin SOIC Package
SNAPHAT (SH)
Crystal/Battery
28
1
SOH28 (MH)
February 2005
1/21







M40Z300MQ1TR pdf, 数据表
M40Z300, M40Z300W
Figure 8. Address-Decode Time
A, B
tAS
E
tEDL
tEDH
E1CON - E4CON
AI02551
Note: During system design, compliance with the SRAM timing parameters must comprehend the propagation delay between E1CON -
E4CON.
Data Retention Lifetime Calculation
Most low power SRAMs on the market today can
be used with the M40Z300/W NVRAM SUPERVI-
SOR. There are, however some criteria which
should be used in making the final choice of which
SRAM to use. The SRAM must be designed in a
way where the chip enable input disables all other
inputs to the SRAM. This allows inputs to the
M40Z300/W and SRAMs to be “Don't Care” once
VCC falls below VPFD(min). The SRAM should also
guarantee data retention down to VCC = 2.0V. The
chip enable access time must be sufficient to meet
the system needs with the chip enable propaga-
tion delays included. If the SRAM includes a sec-
ond chip enable pin (E2), this pin should be tied to
VOUT.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use.
The data retention current value of the SRAMs can
then be added to the IBAT value of the M40Z300/
W to determine the total current requirements for
data retention. The available battery capacity for
the SNAPHAT® of your choice can then be divided
by this current to determine the amount of data re-
tention available (see Table 13., page 19).
CAUTION: Take care to avoid inadvertent dis-
charge through VOUT and E1CON - E4CON after
battery has been attached.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
Power-on Reset Output
All microprocessors have a reset input which forc-
es them to a known state when starting. The
M40Z300/W has a reset output (RST) pin which is
guaranteed to be low within tWPT of VPFD (see 7).
This signal is an open drain configuration. An ap-
propriate pull-up resistor should be chosen to con-
trol the rise time. This signal will be valid for all
voltage conditions, even when VCC equals VSS.
Once VCC exceeds the power failure detect volt-
age VPFD, an internal timer keeps RST low for
tREC to allow the power supply to stabilize.
Battery Low Pin
The M40Z300/W automatically performs battery
voltage monitoring upon power-up, and at factory-
programmed time intervals of at least 24 hours.
The Battery Low (BL) pin will be asserted if the
battery voltage is found to be less than approxi-
mately 2.5V. The BL pin will remain asserted until
completion of battery replacement and subse-
quent battery low monitoring tests, either during
the next power-up sequence or the next scheduled
24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below
2.5V and may not be able to maintain data integrity
in the SRAM. Data should be considered suspect,
and verified as correct. A fresh battery should be
installed.
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal VCC is
supplied. In order to insure data integrity during
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT® top
should be replaced with valid VCC applied to the
device.
8/21







M40Z300MQ1TR equivalent, schematic
M40Z300, M40Z300W
Figure 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Outline
A1 A
A2
A3
eA B L
D eB
E
Note: Drawing is not to scale.
SHZP-A
Table 9. SH – 4-pin SNAPHAT Housing for 48mAh Battery, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min
A 9.78
A1
6.73 7.24
0.265
A2
6.48 6.99
0.255
A3 0.38
B
0.46 0.56
0.018
D
21.21
21.84
0.835
E
14.22
14.99
0.560
eA
15.55
15.95
0.612
eB
3.20 3.61
0.126
L
2.03 2.29
0.080
Max
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
16/21










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