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PDF ( 数据手册 , 数据表 ) M40SZ100

零件编号 M40SZ100
描述 5V or 3V NVRAM SUPERVISOR FOR LPSRAM
制造商 ST Microelectronics
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M40SZ100 数据手册, 描述, 功能
M40SZ100Y
M40SZ100W
5V or 3V NVRAM SUPERVISOR FOR LPSRAM
FEATURES SUMMARY
s CONVERT LOW POWER SRAMs INTO
NVRAMs
s 5V OR 3V OPERATING VOLTAGE
s PRECISION POWER MONITORING and
POWER SWITCHING CIRCUITRY
s AUTOMATIC WRITE-PROTECTION WHEN
VCC IS OUT-OF-TOLERANCE
s CHOICE OF SUPPLY VOLTAGES and
POWER-FAIL DESELECT VOLTAGES:
– M40SZ100Y: VCC = 4.5 to 5.5V;
4.20V VPFD 4.50V
– M40SZ100W: VCC = 2.7 to 3.6V;
2.55V VPFD 2.70V
s RESET OUTPUT (RST) FOR POWER ON
RESET
s 1.25V REFERENCE (for PFI/PFO)
s LESS THAN 10ns CHIP ENABLE ACCESS
PROPAGATION DELAY (at 5V)
s OPTIONAL PACKAGING INCLUDES A 28-
LEAD SOIC and SNAPHAT® TOP (to be
ordered separately)
s 28-LEAD SOIC PACKAGE PROVIDES
DIRECT CONNECTION FOR A SNAPHAT
TOP WHICH CONTAINS THE BATTERY
s BATTERY LOW PIN (BL)
Figure 1. 16-pin SOIC Package
16
1
SO16 (MQ)
Figure 2. 28-pin SOIC Package*
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
* Contact Local Sales Office
September 2003
Rev. 1.3
1/19







M40SZ100 pdf, 数据表
M40SZ100Y, M40SZ100W
OPERATION
The M40SZ100Y/W, as shown in Figure 7, page 5,
can control one (two, if placed in parallel) standard
low-power SRAM. This SRAM must be configured
to have the chip enable input disable all other input
signals. Most slow, low-power SRAMs are config-
ured like this, however many fast SRAMs are not.
During normal operating conditions, the condi-
tioned chip enable (ECON) output pin follows the
chip enable (E) input pin with timing shown in Ta-
ble 6, page 10. An internal switch connects VCC to
VOUT. This switch has a voltage drop of less than
0.3V (IOUT1).
When VCC degrades during a power failure, ECON
is forced inactive independent of E. In this situa-
tion, the SRAM is unconditionally write protected
as VCC falls below an out-of-tolerance threshold
(VPFD). For the M40SZ100Y/W the power fail de-
tection value associated with VPFD is shown in Ta-
ble 5, page 7.
If chip enable access is in progress during a power
fail detection, that memory cycle continues to com-
pletion before the memory is write protected. If the
memory cycle is not terminated within time tWPT,
ECON is unconditionally driven high, write protect-
ing the SRAM. A power failure during a WRITE cy-
cle may corrupt data at the currently addressed
location, but does not jeopardize the rest of the
SRAM's contents. At voltages below VPFD (min),
the user can be assured the memory will be write
protected within the Write Protect Time (tWPT) pro-
vided the VCC fall time does not exceed tF (see Ta-
ble 6, page 10).
As VCC continues to degrade, the internal switch
disconnects VCC and connects the internal battery
to VOUT. This occurs at the switchover voltage
(VSO). Below the VSO, the battery provides a volt-
age VOHB to the SRAM and can supply current
IOUT2 (see Table 5, page 7).
When VCC rises above VSO, VOUT is switched
back to the supply voltage. Output ECON is held in-
active for tCER (120ms maximum) after the power
supply has reached VPFD, independent of the E in-
put, to allow for processor stabilization (see Figure
11, page 10).
Data Retention Lifetime Calculation
Most low power SRAMs on the market today can
be used with the M40SZ100Y/W NVRAM Control-
ler. There are, however some criteria which should
be used in making the final choice of which SRAM
to use. The SRAM must be designed in a way
where the chip enable input disables all other in-
puts to the SRAM. This allows inputs to the
M40SZ100Y/W and SRAMs to be “Don't care”
once VCC falls below VPFD(min) (see Figure 10,
page 9). The SRAM should also guarantee data
retention down to VCC = 2.0V. The chip enable ac-
cess time must be sufficient to meet the system
needs with the chip enable propagation delays in-
cluded.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use. The data retention current value of the
SRAMs can then be added to the ICCDR value of
the M40SZ100Y/W to determine the total current
requirements for data retention. The available bat-
tery capacity for the SNAPHAT® of your choice
(see Table 13, page 17) can then be divided by
this current to determine the amount of data reten-
tion available.
CAUTION: Take care to avoid inadvertent dis-
charge through VOUT and ECON after battery has
been attached.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
8/19







M40SZ100 equivalent, schematic
M40SZ100Y, M40SZ100W
Figure 17. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Outline
A1 A
A2
A3
eA B L
D eB
E
SHZP-A
Note: Drawing is not to scale.
Table 11. SH – 4-pin SNAPHAT Housing for 120mAh Battery, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min
A 10.54
A1
8.00 8.51
0.315
A2
7.24 8.00
0.285
A3 0.38
B
0.46 0.56
0.018
D
21.21
21.84
0.835
E
17.27
18.03
0.680
eA
15.55
15.95
0.612
eB
3.20 3.61
0.126
L
2.03 2.29
0.080
Max
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.628
0.142
0.090
16/19










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