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PDF ( 数据手册 , 数据表 ) MH16V725BWJ-5

零件编号 MH16V725BWJ-5
描述 HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
制造商 Mitsubishi
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MH16V725BWJ-5 数据手册, 描述, 功能
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V725BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH16V725BWJ is 16777216-word x 72-bit dynamic
ram module. This consist of eighteen industry standard
16M x 4 dynamic RAMs in SOJ and one industry standard
EEPROM in TSSOP.
The mounting of SOJs and TSSOP on a card edge dual
in-line package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
/RAS /CAS Address /OE Cycle Power
access access access access
time time time time time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.W)
MH16V725BWJ-5 50 13 25 13 84 5.40
MH16V725BWJ-6 60 15 30 15 104 4.50
PIN CONFIGURATION
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 16M x 4 RAMs in SOJ and industry
standard EEPROM in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
Low stand-by power dissipation
32.4mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH16V725BWJ -5 . . . . . . . . . . . . . . . . . . 6.48W(Max)
MH16V725BWJ -6 . . . . . . . . . . . . . . . . . . 5.84W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 18) decoupling capacitors
4096 refresh cycle every 64ms (CBR Ref)
8192 refresh cycle every 64ms (RAS Only Ref,Normal R/W)
Hyper-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
Gold plating contact pads
Row Address A0 ~ A12
Column Address A0 ~ A10
APPLICATION
Main memory unit for computers , Microcomputer memory
BACK SIDE
124pin 40pin
125pin 41pin
FRONT SIDE
168pin 84pin
MIT-DS-0236-0.0
MITSUBISHI
ELECTRIC
( 1 / 22 )
27/Jul./1998







MH16V725BWJ-5 pdf, 数据表
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V725BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle,
Read Write Mix Cycle,Hi-Z control by /OE or /W) (Note 25)
Symbol
Parameter
tHPC Hyper page mode read/write cycle time
tHPRWC Hyper page mode read write/read modify write cycle time
tDOH Output hold time from /CAS low
tRAS /RAS low pulse width for read write cycle (Note26)
tCP /CAS high pulse width
(Note27)
tCPRH /RAS hold time after /CAS precharge
tCPWD Delay time, /CAS precharge to W low
(Note24)
Limits
-5
Min Max
Min
20 25
55 66
55
65 100000
8 13
28
43
77
10
33
50
-6
Max
100000
16
Unit
ns
ns
ns
ns
ns
ns
ns
tCHOL
tOEPE
tWPE
Hold time to maintain the data Hi-Z until /CAS access
/OE Pulse width (Hi-Z control)
/W Pulse width (Hi-Z control)
7
7
7
7 ns
7 ns
7 ns
tHCWD
tHAWD
tHPWD
Delay time, /CAS low to /W low after read
Delay time, Address to /W low after read
Delay time, /CAS precharge to /W low after read
28
40
43
32
47
50
ns
ns
ns
tHCOD
tHAOD
tHPOD
Delay time, /CAS low to /OE high after read
Delay time, Address to /OE high after read
Delay time, /CAS precharge to /OE high after read
13
25
28
15
30
33
ns
ns
ns
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle.
26: tRAS(min) is specified as two cycles of /CAS input are performed.
27: tCP(max) is specified as a reference point only. If tCP tCP(max),access time is controlled exclusively by tCAC.
/CAS before /RAS Refresh Cycle (Note 28)
Symbol
Parameter
tCSR
tCHR
tRSR
tRHR
/CAS setup time before /RAS low
/CAS hold time after /RAS low
Read setup time before /RAS low
Read hold time after /RAS low
Limits
-5 -6
Min Max
Min Max
55
10 10
10 10
10 10
Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh
mode.
Unit
ns
ns
ns
ns
MIT-DS-0236-0.0
MITSUBISHI
ELECTRIC
( 8 / 22 )
27/Jul./1998







MH16V725BWJ-5 equivalent, schematic
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V725BWJ -5, -6
HYPER PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Hyper Page Mode Mix Cycle (1)
/RAS
/CAS
Address
/W
DQ
(INPUTS)
DQ
(OUTPUTS)
/OE
tRAS
tRP
tRWL
VIH
VIL
tCRP
tCSH
tRCD
tCAS
tHPC
tCP tCAS
tCP
tHPRWC
tCAS
tCRP
VIH
VIL
tRAD
tASR tRAH
tASC
tCAH
tASC tCAH
tASC tCAH
tCWL
tASR
VIH ROW
VIL ADDRESS
COLUMN-1
COLUMN-2
COLUMN-3
ROW
ADDRESS
tRCS
tWCS
tWCH
tCPWD
tAWD
tCAL
tCAL
tCWD
tWP
VIH
VIL
tDZC
tDH tDZ
tDS C
tDS tDH
VIH
VIL
VOH
VOL
VIL
VIH
tCAC
tAA
tCLZ
DATA
VALID-2
tWEZ
Hi-Z
tRAC
tDZO
DATA
VALID-1
tOEA
tOCH
tOEZ
tAA
tCAC
tCLZ
DATA
VALID-3
tCPA
tDZO tOEA tOEZ
DATA
VALID-3
tOEH
Note 30 : /OE=L; /W Hi-Z control
/OE=H; /OE Hi-Z control
tODD
tODD
MIT-DS-0236-0.0
MITSUBISHI
ELECTRIC
( 16 / 22 )
27/Jul./1998










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