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PDF ( 数据手册 , 数据表 ) MH16V724AWJ-5

零件编号 MH16V724AWJ-5
描述 FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
制造商 Mitsubishi
LOGO Mitsubishi LOGO 


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MH16V724AWJ-5 数据手册, 描述, 功能
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V724AWJ -5, -6
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
DESCRIPTION
The MH16V724AWJ is 16777216-word x 64-bit dynamic
ram module. This consist of eighteen industry standard
16M x 4 dynamic RAMs in SOJ and one industry standard
EEPROM in TSSOP.
The mounting of SOJs and TSSOP on a card edge dual
in-line package provides any application where high
densities and large of quantities memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
/RAS /CAS Address /OE Cycle Power
access access access access
time time time time time dissipation
(max.ns) (max.ns) (max.ns) (max.ns) (min.ns) (typ.W)
MH16V724AWJ-5 50 13 25 13 90 7.02
MH16V724AWJ-6 60 15 30 15 110 5.85
PIN CONFIGURATION
85pin 1pin
94pin
95pin
10pin
11pin
Utilizes industry standard 16M x 4 RAMs in SOJ and industry
standard EEPROM in TSSOP
168-pin (84-pin dual dual in-line package)
Single +3.3V(±0.3V) supply operation
Low stand-by power dissipation
19.44mW(Max) . . . . . . . . . . . . . . . . . . . LVCMOS input level
Low operation power dissipation
MH16V724AWJ -5 . . . . . . . . . . . . . . . . . . 8.43W(Max)
MH16V724AWJ -6 . . . . . . . . . . . . . . . . . . 7.78W(Max)
All input are directly LVTTL compatible
All output are three-state and directly LVTTL compatible
Includes(0.22uF x 16) decoupling capacitors
4096 refresh cycle every 64ms
Fast-page mode,Read-modify-write,
/CAS before /RAS refresh,Hidden refresh capabilities
Gold plating contact pads
Row Address A0 ~ A11
Column Address A0 ~ A11
APPLICATION
Main memory unit for computers , Microcomputer memory
BACK SIDE
124pin 40pin
125pin 41pin
FRONT SIDE
168pin 84pin
MIT-DS-0124-0.0
MITSUBISHI
ELECTRIC
( 1 / 20 )
26/Feb./1997







MH16V724AWJ-5 pdf, 数据表
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V724AWJ -5, -6
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Read and Refresh Cycles
Symbol
Parameter
tRC
tRAS
tCAS
tCSH
tRSH
tRCS
tRCH
tRRH
tRAL
Read cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read Setup time after /CAS high
Read hold time after /CAS low
Read hold time after /RAS low
Column address to /RAS hold time
tORH
tOCH
/RAS hold time after /OE low
/CAS hold time after /OE low
Note 21: Either tRCH or tRRH must be satisfied for a read cycle.
Write Cycle (Early Write and Delayed Write)
(Note 21)
(Note 21)
Symbol
Parameter
tWC
tRAS
tCAS
tCSH
tRSH
tWCS
tWCH
tCWL
tRWL
tWP
tDS
tDH
tOEH
Write cycle time
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Write setup time before /CAS low
(Note 23)
Write hold time after /CAS low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
Data setup time before /CAS low or /W low
Data hold time after /CAS low or /W low
/OE hold time after /W low
Read-Write and Read-Modify-Write Cycles
Symbol
Parameter
tRWC
tRAS
tCAS
tCSH
tRSH
tRCS
tCWD
tRWD
tAWD
tOEH
tCWL
tRWL
tWP
tDS
tDH
Read write/read modify write cycle time (Note22)
/RAS low pulse width
/CAS low pulse width
/CAS hold time after /RAS low
/RAS hold time after /CAS low
Read setup time before /CAS low
Delay time, /CAS low to /W low
(Note23)
Delay time, /RAS low to /W low
(Note23)
Delay time, address to /W low
(Note23)
/OE hold time after /W low
/CAS hold time after /W low
/RAS hold time after /W low
Write pulse width
Data setup time before /CAS low or /W low
Data hold time after /CAS low or /W low
Limits
-5 -6
Min
Max
Min
Max
90 110
50
10000
60
10000
15
10000
15
10000
50 60
15 15
00
00
10 10
25 30
13 15
13 15
Limits
-5
Min Max
90
50 10000
15 10000
50
-6
Min Max
110
60 10000
15 10000
60
15 15
00
10 10
15 15
15 15
10 10
00
10 10
13 15
Limits
-5
Min Max Min
130 150
85 10000
95
50 10000
50
85 95
50 50
00
30 30
65 75
40 45
10 15
15 15
15 15
10 10
00
10 10
-6
Max
10000
10000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 22:tRWC is specified as tRWC(min)=tRAC(max)+tODD(min)+tRWL(min)+tRP(min)+4tT.
24:tWCS, tCWD,tRWD ,tAWD and,tCPWD are specified as reference points only. If tWCStWCS(min) the cycle is an early write cycle and the DQ pins will remain
high impedance throughout the entire cycle. If tCWDtCWD(min), tRWDtRWD (min), tAWDtAWD(min) and tCPWD tCPWD(min) (for Hyper page mode cycle only),
the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address. If neither of the above condition (delayed write) of the DQ (at access
time and until /CAS or /OE goes back to VIH) is indeterminate.
MIT-DS-0124-0.0
MITSUBISHI
ELECTRIC
( 8 / 20 )
26/Feb./1997







MH16V724AWJ-5 equivalent, schematic
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI LSIs
MH16V724AWJ -5, -6
FAST PAGE MODE 1207959552 - BIT ( 16777216 - WORD BY 72 - BIT ) DYNAMIC RAM
Fast Page Mode Read Cycle
RAS
VIH
VIL
CAS
VIH
VIL
Address
VIH
VIL
VIH
W
VIL
DQ
(INPUTS)
VIH
VIL
DQ
(OUTPUTS)
VOH
VOL
VIL
OE VIH
tRAS
tRP
tCRP
tCSH
tRCD
tCAS
tPC tRSH
tCP tCAS tCP
tCAS
tASR
tRAD
tRAH
tASC
tCAH
ROW
ADDRESS
COLUMN-1
tRCS
tRCH
tASC tCAH
tCPRH
tASC tCAH
COLUMN-2
tRCS tRCH
COLUMN-3
tRAL
tRCS
tASR
ROW
ADDRESS
tRCH
tRRH
tDZC
tDZC
tDZC
tCDD
Hi-Z
Hi-Z
tCAC
tAA
tOFF
tCLZ
DATA
VALID-1
Hi-Z
tCAC
tAA
tCLZ
tOFF
DATA
VALID-2
tCAC
tAA
tCLZ
tOFF
DATA
VALID-3
tRAC
tDZO
tOEA
tOCH
tCPA
tOEZ
tOEA
tOCH
tCPA
tOEZ
tOEA
tOCH
tOEZ
tDZO
tODD
tDZO
tODD
tORH
tODD
MIT-DS-0124-0.0
MITSUBISHI
ELECTRIC
( 16 / 20 )
26/Feb./1997










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