DataSheet8.cn


PDF ( 数据手册 , 数据表 ) MH16S72DDFA-8

零件编号 MH16S72DDFA-8
描述 1 /207 /959 /552-BIT ( 16 /777 /216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
制造商 Mitsubishi
LOGO Mitsubishi LOGO 


1 Page

No Preview Available !

MH16S72DDFA-8 数据手册, 描述, 功能
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72DDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH16S72DDFA is 16777216 - word x 72-bit
Sy nchronous DRAM module. This consist of eighteen
industry standard 16M x 4 Sy nchronous DRAMs in
TSOP.
The TSOP on a card edge dual in-line package prov ides
any application where high densities and large of
quantities memory are required.
This is a socket-ty pe memory m odule ,suitable f or
easy interchange or addition of m odule.
FEATURES
Type name
Max.
Frequency
CLK
Access Time
[component level]
MH16S72DDFA-7
MH16S72DDFA-8
100MHz
100MHz
6ns (CL = 2, 3)
6ns (CL = 3)
Utilizes industrystandard 16M X 4 Synchronous DRAMs in
TSOP package , industry standard Resistered buffer in TSSOP
package and industrystandard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst W rite / Single W rite(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every64ms
Discrete IC and module design conform to
PC/100 specification.
(module Spec. Rev. 1.2 and SPD 1.2A)
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
APPLICATION
Main memory unit for computers, Microcomputer memory.
168pin 84pin
MIT-DS-0347-0.1
MITSUBISHI
ELECTRIC
15/Oct./1999 1







MH16S72DDFA-8 pdf, 数据表
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72DDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
WRITE
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
/S /RAS /CAS /WE Address
Command
Action
H X X XX
DESEL NOP(Continue Burst to END)
L H H HX
NOP
NOP(Continue Burst to END)
L H H L BA
TBST
Terminate Burst
Terminate Burst,Latch CA,
L H L H BA,CA,A10 READ/READA Begin Read,Determine Auto-
Precharge*3
Terminate Burst,Latch CA,
L
HL
L BA,CA,A10
WRITE/
Begin Write,Determine Auto-
WRITEA Precharge*3
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA Terminate Burst,Precharge
L L L HX
Op-Code,
LLLL
Mode-Add
REFA
MRS
ILLEGAL
ILLEGAL
H X X XX
DESEL NOP(Continue Burst to END)
L H H HX
NOP
NOP(Continue Burst to END)
L H H L BA
TBST
ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
WRITE/
L H L L BA,CA,A10
ILLEGAL
WRITEA
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
L
L
L
Op-Code,
L
Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP(Continue Burst to END)
L H H HX
NOP
NOP(Continue Burst to END)
L H H L BA
TBST
ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
WRITE/
L H L L BA,CA,A10
ILLEGAL
WRITEA
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
MIT-DS-0347-0.1
MITSUBISHI
ELECTRIC
15/Oct./1999 8







MH16S72DDFA-8 equivalent, schematic
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72DDFA-7, -8
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70°C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Tim ing Measurement Level: 1.4V
LATCH MODE
Symbol Parameter
tCLK
tCH
tCL
tT
tIS
tIH
tRC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tPDE
tREF
CK cycle time
CL=3
CL=4
CK High pulse width
CK Low pilse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row cycle tim e
Row to Column Delay
Row Active tim e
Row Precharge time
Write Recovery time
Act to Act Deley tim e
Mode Register Set Cycle tim e
Self Refresh Exit time
Power Down Exit tim e
Refresh Interval time
Limits
-7 -8
Min. Max. Min.
Max.
10 13
10 10
33
33
1 10 1
10
22
11
70 70
20 20
50 100000 50 100000
20 20
20 20
20 20
10 10
10 10
10 10
64 64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns
should be added to the parameter.
CK
Signal
1.4V Any AC timing is
referenced to the input
signal crossing
through 1.4V.
1.4V
MIT-DS-0347-0.1
MITSUBISHI
ELECTRIC
15/Oct./1999 16










页数 30 页
下载[ MH16S72DDFA-8.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
MH16S72DDFA-71 /207 /959 /552-BIT ( 16 /777 /216-WORD BY 72-BIT ) Synchronous DYNAMIC RAMMitsubishi
Mitsubishi
MH16S72DDFA-81 /207 /959 /552-BIT ( 16 /777 /216-WORD BY 72-BIT ) Synchronous DYNAMIC RAMMitsubishi
Mitsubishi

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap