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PDF ( 数据手册 , 数据表 ) MH16S72DCFA-6

零件编号 MH16S72DCFA-6
描述 1 /207 /959 /552-BIT ( 16 /777 /216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
制造商 Mitsubishi
LOGO Mitsubishi LOGO 


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MH16S72DCFA-6 数据手册, 描述, 功能
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72DCFA-6
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH16S72DCFA is 16777216 - word x 72-bit Sy nchronous
DRAM module. This consist of eighteen industry standard
16M x 4 Sy nchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package prov ides any
application where high densities and large of quantities memory
are required.
This is a socket-ty pe memory module ,suitable f or easy
interchange or addition of module.
FEATURES
Type name
Max.
Frequency
Access Time from CLK
[component level]
MH16S72DCFA-6
133MHz
5.4ns
(CL = 4 at Latch mode)
Utilizes industry standard 16M X 4 Synchronous DRAMs in
TSOP package , industrystandard Resistered buffer in TSSOP
package,industrystandard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
Max.Clock frequency 133MHz
Fullysynchronous operation referenced to clock rising edge
4-bank operation controlled byBA0,BA1(Bank Address)
/CAS latency-2/3(programmable,at buffer mode)
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst type- Sequential and interleave burst (programmable)
Random column access
Burst W rite / Single W rite(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC133 specification.
APPLICATION
Main memoryor graphic memoryin computer systems
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
MIT-DS-0349-0.1
MITSUBISHI
ELECTRIC
15/Oct. /1999 1







MH16S72DCFA-6 pdf, 数据表
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72DCFA-6
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
WRITE
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
/S /RAS /CAS /WE Address
Command
Action
H X X XX
DESEL NOP(Continue Burst to END)
L H H HX
NOP
NOP(Continue Burst to END)
L H H L BA
TBST
Terminate Burst
Terminate Burst,Latch CA,
L H L H BA,CA,A10 READ/READA Begin Read,Determine Auto-
Precharge*3
Terminate Burst,Latch CA,
L H L L BA,CA,A10 WRITE/ Begin Write,Determine Auto-
WRITEA Precharge*3
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA Terminate Burst,Precharge
L L L HX
Op-Code,
LLLL
Mode-Add
H X X XX
REFA
MRS
DESEL
ILLEGAL
ILLEGAL
NOP(Continue Burst to END)
L H H HX
NOP
NOP(Continue Burst to END)
L H H L BA
TBST
ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
WRITE/
L H L L BA,CA,A10
ILLEGAL
WRITEA
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
L L L L Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP(Continue Burst to END)
L H H HX
L H H L BA
NOP
TBST
NOP(Continue Burst to END)
ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10 WRITE/ ILLEGAL
WRITEA
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
L L L L Mode-Add
MRS
ILLEGAL
MIT-DS-0349-0.1
MITSUBISHI
ELECTRIC
15/Oct. /1999 8







MH16S72DCFA-6 equivalent, schematic
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72DCFA-6
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Tim ing Measurement Level: 1.4V
LATCH MODE
Symbol Parameter
tCLK CK cycle time
tCH
tCL
tT
tIS
tIH
tRC
tRFC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tPDE
tREF
CK High pulse width
CK Low pulse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row Cycle tim e
Row Refresh Cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery tim e
Act to Act Deley time
Mode Register Set Cycle tim e
Self Refresh Exit tim e
Power Down Exit time
Refresh Interval time
CL=3
CL=4
Limits
Min.
10
7.5
2.5
2.5
1
1.5
0.8
67.5
75
20
45
20
15
15
10
7.5
7.5
Max.
10
100K
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note:1 The timing requirements are assumed tT=1ns.If tT is longer than 1ns,(tT-1)ns
should be added to the parameter.
CK
Signal
1.4V Any AC timing is
referenced to the input
signal crossing
1.4V through 1.4V.
MIT-DS-0349-0.1
MITSUBISHI
ELECTRIC
15/Oct. /1999 16










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