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PDF ( 数据手册 , 数据表 ) MH16S72DAMD-8

零件编号 MH16S72DAMD-8
描述 1207959552-BIT (16777216 - WORD BY 72-BIT)Synchronous DRAM
制造商 Mitsubishi
LOGO Mitsubishi LOGO 


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MH16S72DAMD-8 数据手册, 描述, 功能
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72DAMD -6,-7,-8
1207959552-BIT (16777216 - WORD BY 72-BIT)Synchronous DRAM
DESCRIPTION
The MH16S72DAMD is 16777216 - word by 72-bit
Synchronous DRAM module. This consists of
eighteen industry standard 8Mx8 Synchronous
DRAMs in TSOP and one industory standard
EEPROM in TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-6 133MHz 5.4ns(CL=3)
-7 100MHz 6.0ns(CL=2)
-8 100MHz 6.0ns(CL=3)
Utilizes industry standard 8M x 8 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock
rising edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100/PC133 specification.
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
APPLICATION
PC main memory
MIT-DS-0336-0.0
MITSUBISHI
ELECTRIC
( 1 / 55 )
23.Sep.1999







MH16S72DAMD-8 pdf, 数据表
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72DAMD -6,-7,-8
1207959552-BIT (16777216 - WORD BY 72-BIT)Synchronous DRAM
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
MNEMONIC
CKE
n-1
CKE
n
/S
/RAS /CAS /WE BA0,1 A11
A10 A0-9
DESEL
NOP
H XHX X X X X X X
H XL H H H X X X X
Row Adress Entry &
Bank Activate
ACT
H XL L H H V V V V
Single Bank Precharge
Precharge All Bank
Column Address Entry
& Write
PRE
PREA
WRIT E
H XL L
H XL L
HL
HL
H XL
HL
L
VXL X
X X HX
VVL V
Column Address Entry
& Write with Auto- WRITEA H X L H L L V V H V
Precharge
Column Address Entry
& Read
READ
H XL H L H V V L V
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
READA
REFA
REFS
REFSX
Burst Terminate
Mode Register Set
TERM
MRS
H XL H L H V V H V
H HL L L H X X X X
H LL L L H X X X X
L HH X X X X X X X
L HL H H H X X X X
H XL H H L X X X X
H X L L L L L L L V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0336-0.0
MITSUBISHI
ELECTRIC
( 8 / 55 )
23.Sep.1999







MH16S72DAMD-8 equivalent, schematic
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S72DAMD -6,-7,-8
1207959552-BIT (16777216 - WORD BY 72-BIT)Synchronous DRAM
CK
Command
Address
DQ
Read
Y
Q0 Q1 Q2 Q3
Write
Y
D0 D1 D2 D3
CL= 3
BL= 4
/CAS Latency
Burst Length
Burst Type
Burst Length
Initial Address BL
Column Addressing
A2 A1 A0
Sequential
Interleaved
0 00
01 2345 67 0123 4567
0 01
12 3456 70 1032 5476
0 10
23 4567 01 2301 6745
0 11
34 5670 12 3210 7654
8
1 00
45 6701 23 4567 0123
1 01
56 7012 34 5476 1032
1 10
67 0123 45 6745 2301
1 11
70 1234 56 7654 3210
- 00
01 23
0 12 3
- 01
12 30
4
- 10
23 01
1 03 2
2 30 1
- 11
30 12
3 21 0
- -0
01
2
- -1
10
01
10
MIT-DS-0336-0.0
MITSUBISHI
ELECTRIC
( 16 / 55 )
23.Sep.1999










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