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PDF ( 数据手册 , 数据表 ) MH16S72BAMD-6

零件编号 MH16S72BAMD-6
描述 1 /207 /959 /552-BIT ( 16 /777 /216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
制造商 Mitsubishi
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MH16S72BAMD-6 数据手册, 描述, 功能
MITSUBISHI LSIs
MH16S72BAMD-6
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
PRELIMINARY
Some of contents are subject to change without notice.
DESCRIPTION
The MH16S72BAMD is 16777216 - word x 72-bit
Synchronous DRAM module. This consist of eighteen
industry standard 8M x 8 Synchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package provides any
application where high densities and large of quantities
memory are required.
This is a socket-type memory module ,suitable for easy
interchange or addition of module.
FEATURES
Type name
Max.
Frequency
Access Time from CLK
[component level]
MH16S72BAMD-6
133MHz
5.4ns
(CL = 3)
85pin
94pin
95pin
1pin
10pin
11pin
Utilizes industry standard 8M X 8 Synchronous DRAMs in TSOP
package
Single 3.3V +/- 0.3V supply
Max.Clock frequency 133MHz
Fully synchronous operation referenced to clock rising edge
4-bank operation controlled by BA0,BA1(Bank Address)
/CAS latency -2/3(programmable,at buffer mode)
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst type- Sequential and interleave burst (programmable)
Random column access
Burst Write / Single Write(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
124pin 40pin
125pin 41pin
APPLICATION
Main memory or graphic memory in computer systems
168pin 84pin
MIT-DS-0314-0.0
MITSUBISHI
ELECTRIC
10/May. /1999 1







MH16S72BAMD-6 pdf, 数据表
MITSUBISHI LSIs
MH16S72BAMD-6
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE(continued)
Current State
WRITE
READ with
AUTO
PRECHARGE
WRITE with
AUTO
PRECHARGE
/S /RAS /CAS /WE Address
Command
Action
H X X XX
DESEL NOP(Continue Burst to END)
L H H HX
NOP
NOP(Continue Burst to END)
L H H L BA
TBST
Terminate Burst
Terminate Burst,Latch CA,
L H L H BA,CA,A10 READ/READA Begin Read,Determine Auto-
Precharge*3
Terminate Burst,Latch CA,
L H L L BA,CA,A10
WRITE/ Begin Write,Determine Auto-
WRITEA Precharge*3
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA Terminate Burst,Precharge
L L L HX
Op-Code,
LLLL
Mode-Add
H X X XX
REFA
MRS
DESEL
ILLEGAL
ILLEGAL
NOP(Continue Burst to END)
L H H HX
NOP
NOP(Continue Burst to END)
L H H L BA
TBST
ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
WRITE/
L H L L BA,CA,A10
ILLEGAL
WRITEA
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
L L L L Mode-Add
MRS
ILLEGAL
H X X XX
DESEL NOP(Continue Burst to END)
L H H HX
L H H L BA
NOP
TBST
NOP(Continue Burst to END)
ILLEGAL
L H L H BA,CA,A10 READ/READA ILLEGAL
L H L L BA,CA,A10
WRITE/ ILLEGAL
WRITEA
L L H H BA,RA
ACT
Bank Active/ILLEGAL*2
L L H L BA,A10
PRE/PREA ILLEGAL*2
L L L HX
REFA
ILLEGAL
Op-Code,
L L L L Mode-Add
MRS
ILLEGAL
MIT-DS-0314-0.0
MITSUBISHI
ELECTRIC
10/May. /1999 8







MH16S72BAMD-6 equivalent, schematic
MITSUBISHI LSIs
MH16S72BAMD-6
1,207,959,552-BIT ( 16,777,216-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
AC TIMING REQUIREMENTS
(Ta=0 ~ 70C, Vdd = 3.3 +/- 0.3V, Vss = 0V, unless otherwise noted)
Input Pulse Levels:
0.8V to 2.0V
Input Timing Measurement Level: 1.4V
Symbol Parameter
tCLK CK cycle time
tCH
tCL
tT
tIS
tIH
tRC
tRFC
tRCD
tRAS
tRP
tWR
tRRD
tRSC
tSRX
tPDE
tREF
CK High pulse width
CK Low pulse width
Transition time of CK
Input Setup time(all inputs)
Input Hold time(all inputs)
Row Cycle time
Row Refresh Cycle time
Row to Column Delay
Row Active time
Row Precharge time
Write Recovery time
Act to Act Deley time
Mode Register Set Cycle time
Self Refresh Exit time
Power Down Exit time
Refresh Interval time
CL=3
CL=2
Limits
Min.
7.5
-
2.5
2.5
1
1.5
0.8
67.5
80
22.5
45
22.5
15
15
15
7.5
7.5
Max.
10
100K
64
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
CK
Signal
MIT-DS-0314-0.0
1.4V Any AC timing is
referenced to the input
signal crossing
1.4V through 1.4V.
MITSUBISHI
ELECTRIC
10/May. /1999 16










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