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PDF ( 数据手册 , 数据表 ) MH16S64FFB-10

零件编号 MH16S64FFB-10
描述 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
制造商 Mitsubishi
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MH16S64FFB-10 数据手册, 描述, 功能
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH16S64FFB is 16777216 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 16Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
-10,10L 100MHz
CLK Access Time
(Component SDRAM)
8.0ns(CL=3)
Utilizes industry standard 16M x 8 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
1
2
MIT-DS-0280-0.1
MITSUBISHI
ELECTRIC
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15. Jan.1999







MH16S64FFB-10 pdf, 数据表
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
MNEMONIC
CKE
n-1
CKE
n
/S0
/RAS /CAS
/WE BA0,1
A11
A10 A0-9
DESEL
NOP
H XHX X X X X X X
H XL H H H X X X X
Row Adress Entry &
Bank Activate
ACT
H XL L H H V V V V
Single Bank Precharge
Precharge All Bank
Column Address Entry
& Write
PRE
PREA
WRITE
H XL L
H XL L
HL
HL
H XL H L L
VXL X
XXHX
VXL V
Column Address Entry
& Write with Auto-
WRITEA H X L H L L V X H V
Precharge
Column Address Entry
& Read
READ
H XL H L H V X L V
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Burst Terminate
Mode Register Set
READA
REFA
REFS
REFSX
TERM
MRS
H XL H L H V X H V
H HL L L H X X X X
H LLL L H X X X X
L HHX X X X X X X
L HL H H H X X X X
H XL H H L X X X X
H X L L L L L L L V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0280-0.1
MITSUBISHI
ELECTRIC
( 8 / 55 )
15. Jan.1999







MH16S64FFB-10 equivalent, schematic
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64FFB -10,-10L
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
[ /CAS LATENCY]
/CAS latency,CL,is used to synchronize the first output data with the CLK frequency,i.e.,the
speed of CLK determines which CL should be used.First output data is available after CL
cycles from READ command.
/CAS Latency Timing(BL=4)
CK
Command
Address
DQ
DQ
ACT
X
tRCD
READ
Y
CL=2
Q0 Q1 Q2 Q3
CL=3
Q0 Q1 Q2 Q3
CL=2
CL=3
[ BURST LENGTH ]
The burst length,BL,determines the number of consecutive wrutes or reads that will be
automatically performed after the initial write or read command.For BL=1,2,4,8,full page the
output data is tristated(Hi-Z) after the last read.For BL=FP (Full Page),the TBST (Burst
Terminate) command should be issued to stop the output of data.
Burst Length Timing(CL=2)
tRCD
CK
Command
ACT
READ
Address
XY
DQ Q0
BL=1
DQ Q0 Q1
BL=2
DQ Q0 Q1 Q2 Q3
BL=4
DQ Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
BL=8
DQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
Qm Q0 Q1 BL=FP
MIT-DS-0280-0.1
m=1023
MITSUBISHI
ELECTRIC
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15. Jan.1999










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