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PDF ( 数据手册 , 数据表 ) MH16S64AMA-8

零件编号 MH16S64AMA-8
描述 1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
制造商 Mitsubishi
LOGO Mitsubishi LOGO 


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MH16S64AMA-8 数据手册, 描述, 功能
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH16S64AMA is 16777216 - word by 64-bit
Synchronous DRAM module. This consists of sixteen
industry standard 16Mx4 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual Inline
package provides any application where high
densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable for
easy interchange or addition of modules.
FEATURES
Frequency
-8 125MHz
CLK Access Time
(Component SDRAM)
6ns(CL=3)
-10 100MHz
8ns(CL=3)
85pin 1pin
94pin
95pin
10pin
11pin
-12 83MHz
8ns(CL=3)
Utilizes industry standard 16M x 4 Synchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 125MHz/100MHz/83MHz
Fully synchronous operation referenced to clock rising
edge
Dual bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
124pin 40pin
125pin 41pin
168pin 84pin
APPLICATION
main memory or graphic memory in computer systems
MIT-DS-0127-0.0
MITSUBISHI
ELECTRIC
( 1 / 52 )
4. Mar.1997







MH16S64AMA-8 pdf, 数据表
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
COMMAND TRUTH TABLE
COMMAND
Deselect
No Operation
MNEMONIC
CK
n-1
DESEL
NOP
H
H
CK
n
X
X
/S /RAS /CAS /WE BA
HX X X X
LH H H X
A10
A0-9
,A11
XX
XX
Row Adress Entry &
Bank Activate
ACT
H XL L H H V V V
Single Bank Precharge
Precharge All Bank
Column Address Entry
& Write
PRE
PREA
WRITE
H XL L H L
H XL L H L
H X L LH H L
VL X
VHX
VL V
Column Address Entry
& Write with Auto-
WRITEA H X L H L L V H V
Precharge
Column Address Entry
& Read
READ
H XL H L H V L V
Column Address Entry
& Read with Auto
Precharge
Auto-Refresh
Self-Refresh Entry
Self-Refresh Exit
Burst Terminate
Mode Register Set
READA
REFA
REFS
REFSX
TERM
MRS
H XL H L H V H V
H H L HL L H X X X
H LL L L H X X X
L H H LX X X X X X
L HL H H H X X X
H XL H H L X X X
H X L L L L L L V*1
H =High Level, L = Low Level, V = Valid, X = Don't Care, n = CK cycle number
NOTE:
1.A7-9 = 0, A0-6 = Mode Address
MIT-DS-0127-0.0
MITSUBISHI
ELECTRIC
( 8 / 52 )
4. Mar.1997







MH16S64AMA-8 equivalent, schematic
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16S64AMA -8,-10,-12
1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM
CK
Command
Address
DQ
Read
Y
Q0 Q1 Q2 Q3
Write
Y
D0 D1 D2 D3
CL= 3
BL= 4
/CAS Latency
Burst Length
Burst Type
Burst Length
Initial Address BL
Column Addressing
A2 A1 A0
Sequential
Interleaved
0 00
01 2 34 5 67 0 12 3 4 56 7
0 01
12 3 45 6 70 1 03 2 5 47 6
0 10
23 4 56 7 01 2 30 1 6 74 5
0 11
34 5 67 0 12 3 21 0 7 65 4
8
1 00
45 6 70 1 23 4 56 7 0 12 3
1 01
56 7 01 2 34 5 47 6 1 03 2
1 10
67 0 12 3 45 6 74 5 2 30 1
1 11
70 1 23 4 56 7 65 4 3 21 0
- 00
01 2 3
0 12 3
- 01
12 3 0
4
- 10
23 0 1
1 03 2
2 30 1
- 11
30 1 2
3 21 0
- -0
01
2
- -1
10
01
10
MIT-DS-0127-0.0
MITSUBISHI
ELECTRIC
( 16 / 52 )
4. Mar.1997










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