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PDF ( 数据手册 , 数据表 ) MH16D64AKQC-75

零件编号 MH16D64AKQC-75
描述 1 /073 /741 /824-BIT (16 /777 /216-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
制造商 Mitsubishi
LOGO Mitsubishi LOGO 


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MH16D64AKQC-75 数据手册, 描述, 功能
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16D64AKQC-75,-10
1,073,741,824-BIT (16,777,216-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
The MH16D64AKQC is 16777216 - word x 64-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 8 industry standard 8M x 16 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
FEATURES
Type name
Max.
Frequency
MH16D64AKQC-75
MH16D64AKQC-10
133MHz
100MHz
CLK
Access Time
[component level]
+ 0.75ns
+ 0.8ns
- Utilizes industry standard 8M X 16 DDR Synchronous DRAMs
in TSOP package , industry standard EEPROM(SPD) in
TSSOP package
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per
clock cy c le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CLK and /CLK)
- data and data mask ref erenced to both edges of DQS
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cy c les /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-8
- SSTL_2 Interf ace
- Module 2bank Conf igration
- Burst Ty pe - sequential/interleav e(programmable)
- Commands entered on each positiv e CLK edge
APPLICATION
Main memoryunit for Note PC, Mobile etc.
PCB Outline
(Front)
(Back)
1
2
199
200
MIT-DS-0400-0.0
MITSUBISHI
ELECTRIC
2.Nov.2000
1







MH16D64AKQC-75 pdf, 数据表
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16D64AKQC-75,-10
1,073,741,824-BIT (16,777,216-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State /S /RAS /CAS /WE
Address
Command
Action
Notes
WRIT E
H X X XX
DESEL NOP (Continue Burst to END)
(Auto-
L H H HX
NOP
NOP (Continue Burst to END)
Precharge L H H L BA
Di sa b l e d )
TERM
ILLEGAL
Terminate Burst, Latch CA,
L H L H BA, CA, A10 READ / READA Begin Read, Determine Auto- 3
Precharge
L H L L BA, CA, A10
WRITE /
WRITEA
Terminate Burst, Latch CA,
Begin Write, Determine Auto-
Precharge
3
L L H H BA, RA
ACT
Bank Active / ILLEGAL
2
L L H L BA, A10
L L L HX
PRE / PREA Terminate Burst, Precharge
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
READ with H X X X X
AUTO
L H H HX
PRECHARGE L H H L BA
DESEL
NOP
TERM
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
L H L H BA, CA, A10 READ / READA ILLEGAL
L H L L BA, CA, A10
WRITE /
WRITEA
ILLEGAL
L L H H BA, RA
ACT
Bank Active / ILLEGAL
L L H L BA, A10
PRE / PREA PRECHARGE/ILLEGAL
2
2
L L L HX
REFA
ILLEGAL
Op-Code,
LLLL
Mode-Add
MRS
ILLEGAL
WRITE with H X X X X
AUTO
L H H HX
PRECHARGE L H H L BA
DESEL
NOP
TERM
NOP (Continue Burst to END)
NOP (Continue Burst to END)
ILLEGAL
L H L H BA, CA, A10 READ / READA ILLEGAL
L H L L BA, CA, A10
WRITE /
WRITEA
ILLEGAL
L L H H BA, RA
ACT
Bank Active / ILLEGAL
L L H L BA, A10
PRE / PREA PRECHARGE/ILLEGAL
2
2
L L L HX
Op-Code,
L L L L Mode-Add
REFA
MRS
ILLEGAL
ILLEGAL
MIT-DS-0400-0.0
MITSUBISHI
ELECTRIC
2.Nov.2000
8







MH16D64AKQC-75 equivalent, schematic
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH16D64AKQC-75,-10
1,073,741,824-BIT (16,777,216-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
ABSOLUTE M AXIMUM RATINGS
Symbol
Vdd
VI
VO
IO
Pd
Topr
T stg
Parameter
Conditions
Supply Voltage
with respect to Vss
Input Voltage
with respect to Vss
Output Voltage
with respect to Vss
Output Current
Power Dissipation
Ta = 25 C
Operating Temperature
Storage Temperature
Ratings
-0.5 ~ 3.7
-0.5 ~ Vdd+0.5
-0.5 ~ Vdd+0.5
50
8
0 ~ 70
-45 ~ 100
Unit
V
V
V
mA
W
C
C
DC OPERATING CONDITIONS
(Ta=0 ~ 70OC , unless otherwise noted)
Symbol
Parameter
Min.
Limits
Typ.
Max.
Unit Notes
Vdd
Vref
Supply Voltage
Input Reference Voltage
2.3
0.49*Vdd
2.5
0.5*Vdd
2.7 V
0.51*Vdd V
5
VIH(DC)
High-Level Input Voltage
Vref + 0.18
Vdd+0.3 V
VIL(DC)
Low-Level Input Voltage
-0.3
Vref - 0.18 V
VIN(DC) Input Voltage Level, CK0 and /CK0
-0.3
Vdd + 0.3 V
VID(DC) Input Differential Voltage, CK0 and /CK0 0.36
Vdd + 0.6 V 7
VTT
I/O Termination Voltage
Vref - 0.04
Vref + 0.04 V 6
CAPACITANCE
(Ta=0 ~ 70OC, Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, unless otherwise noted)
Symbol
Parameter
Test Condition
CI(A) Input Capacitance, address pin
CI(C) Input Capacitance, control pin
CI(K) Input Capacitance, CK0 pin
CI/O Input Capacitance, I/O pin
VI - 1.25V
f =100MHz
VI = 25mVrm
Limits(max.)
45
45
30
20
Unit Notes
pF 11
pF 11
pF 11
pF 11
MIT-DS-0400-0.0
MITSUBISHI
ELECTRIC
2.Nov.2000
16










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Mitsubishi

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