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PDF ( 数据手册 , 数据表 ) M95256-RDL1T

零件编号 M95256-RDL1T
描述 256/128 Kbit Serial SPI Bus EEPROM With High Speed Clock
制造商 ST Microelectronics
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M95256-RDL1T 数据手册, 描述, 功能
M95256
M95128
256/128 Kbit Serial SPI Bus EEPROM
With High Speed Clock
PRELIMINARY DATA
s SPI Bus Compatible Serial Interface
s Supports Positive Clock SPI Modes
s 5 MHz Clock Rate (maximum)
s Single Supply Voltage:
– 4.5V to 5.5V for M95xxx
– 2.7V to 3.6V for M95xxx-V
– 2.5V to 5.5V for M95xxx-W
– 1.8V to 3.6V for M95xxx-R
s Status Register
s Hardware and Software Protection of the Status
Register
s BYTE and PAGE WRITE (up to 64 Bytes)
s Self-Timed Programming Cycle
s Resizeable Read-Only EEPROM Area
s Enhanced ESD Protection
s 100,000 Erase/Write Cycles (minimum)
s 40 Year Data Retention (minimum)
DESCRIPTION
These SPI-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 32K x 8 bits (M95256) and 16K x 8
bits (M95128), and operate down to 2.7 V (for the
8
1
PSDIP8 (BN)
0.25 mm frame
8
1
SO8 (MN)
150 mil width
Figure 1. Logic Diagram
VCC
14
1
TSSOP14 (DL)
169 mil width
8
1
SO8 (MW)
200 mil width
Table 1. Signal Names
C Serial Clock
D Serial Data Input
Q Serial Data Output
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
D
C
S
W
HOLD
M95xxx
VSS
Q
AI01789C
March 2000
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/21







M95256-RDL1T pdf, 数据表
M95256, M95128
Figure 9. Read EEPROM Array Operation Sequence
S
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30
C
INSTRUCTION
16 BIT ADDRESS
D 15 14 13 3 2 1 0
HIGH IMPEDANCE
Q
DATA OUT
76543210
MSB
AI01793
Note: 1. Depending on the memory size, as shown in Table 7, the most significant address bits are Don’t Care.
Table 7. Address Range Bits
Device
M95256
M95128
Address Bits
A14-A0
A13-A0
Note: 1. b15 is Don’t Care on the M95256 series.
b15 and b14 are Don’t Care on the M95128 series.
appropriate area of the memory. When it has
finished, the appropriate values are written to the
BP1, BP0 and SRWD bits, thereby putting the
device in the hardware protected mode.
An alternative method is to write the protected
data, and to set the BP1, BP0 and SRWD bits,
before soldering the memory device to the board.
Again, this results in the memory device being
placed in its hardware protected mode.
If the W pin has been connected to VSS by a pull-
down resistor, the memory device can be taken
out of the hardware protected mode by driving the
W pin high, to override the pull-down resistor.
If the W pin has been directly soldered to VSS,
there is only one way of taking the memory device
out of the hardware protected mode: the memory
device must be de-soldered from the board, and
connected to external equipment in which the W
pin is allowed to be taken high.
Read Operation
The chip is first selected by holding S low. The
serial one byte read instruction is followed by a two
byte address (A15-A0), each bit being latched-in
during the rising edge of the clock (C).
The data stored in the memory, at the selected
address, is shifted out on the Q output pin. Each
bit is shifted out during the falling edge of the clock
(C) as shown in Figure 9. The internal address
counter is automatically incremented to the next
higher address after each byte of data has been
shifted out. The data stored in the memory, at the
Figure 10. Write Enable Latch Sequence
S
01234567
C
INSTRUCTION
D
HIGH IMPEDANCE
Q
AI02281B
8/21







M95256-RDL1T equivalent, schematic
M95256, M95128
Table 14. PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
Symb.
Typ.
mm
Min.
Max.
Typ.
A
3.90
5.90
A1 0.49
A2
3.30
5.30
B
0.36
0.56
B1
1.15
1.65
C
0.20
0.36
D
9.20
9.90
E
7.62
– 0.300
E1
6.00
6.70
e1
2.54
– 0.100
eA 7.80 –
eB 10.00
L
3.00
3.80
N8
inches
Min.
0.154
0.019
0.130
0.014
0.045
0.008
0.362
0.236
0.307
0.118
8
Max.
0.232
0.209
0.022
0.065
0.014
0.390
0.264
0.394
0.150
Figure 17. PSDIP8 (BN)
A2 A
A1 L
B e1
B1
D
N
E1 E
1
Note: 1. Drawing is not to scale.
16/21
C
eA
eB
PSDIP-a










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