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PDF ( 数据手册 , 数据表 ) MC-4532CD647XFA

零件编号 MC-4532CD647XFA
描述 32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE
制造商 Elpida Memory
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MC-4532CD647XFA 数据手册, 描述, 功能
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532CD647XFA
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-4532CD647XFA is 33,554,432 words by 64 bits synchronous dynamic RAM module on which 16 pieces of
128M SDRAM: µPD45128841 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
33,554,432 words by 64 bits organization
Clock frequency and access time from CLK.
Part number
MC-4532CD647XFA-A75
/CAS latency
CL = 3
CL = 2
Clock frequency
(MAX.)
133 MHz
100 MHz
Access time from CLK
(MAX.)
5.4 ns
6.0 ns
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0 and BA1 (Bank Select)
Programmable burst-length (1, 2, 4, 8 and full page)
Programmable wrap sequence (Sequential / Interleave)
Programmable /CAS latency (2, 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
All DQs have 10 Ω ±10 % of series resistor
Single 3.3 V ± 0.3 V power supply
LVTTL compatible
4,096 refresh cycles/64 ms
Burst termination by Burst Stop command and Precharge command
168-pin dual in-line memory module (Pin pitch = 1.27 mm)
Unbuffered type
Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0230N20 (Ver 2.0)
Date Published June 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.







MC-4532CD647XFA pdf, 数据表
MC-4532CD647XFA
Synchronous Characteristics
Parameter
Symbol
Clock cycle time
/CAS latency = 3
/CAS latency = 2
Access time from CLK
/CAS latency = 3
/CAS latency = 2
CLK high level width
CLK low level width
Data-out hold time
Data-out low-impedance time
Data-out high-impedance time /CAS latency = 3
/CAS latency = 2
Data-in setup time
Data-in hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
CKE setup time (Power down exit)
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
Note 1. Output load
Output
tCK3
tCK2
tAC3
tAC2
tCH
tCL
tOH
tLZ
tHZ3
tHZ2
tDS
tDH
tAS
tAH
tCKS
tCKH
tCKSP
tCMS
tCMH
Z = 50
MIN.
7.5
10
2.5
2.5
3.0
0
3.0
3.0
1.5
0.8
1.5
0.8
1.5
0.8
1.5
1.5
-A 75
MAX.
(133 MHz)
(100 MHz)
5.4
6.0
5.4
6.0
0.8
50 pF
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
1
1
Remark These specifications are applied to the monolithic device.
8 Data Sheet E0230N20 (Ver. 2.0)














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