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零件编号 | TDA10021HT | ||
描述 | DVB-C channel receiver | ||
制造商 | NXP Semiconductors | ||
LOGO | |||
1 Page
INTEGRATED CIRCUITS
DATA SHEET
TDA10021HT
DVB-C channel receiver
Product specification
Supersedes data of 2000 Jun 21
File under Integrated Circuits, IC02
2001 Oct 01
Philips Semiconductors
DVB-C channel receiver
Product specification
TDA10021HT
CHARACTERISTICS
SYMBOL
VDDD33
VDDD18
VDDD50
PARAMETER
digital supply voltage for the
pads
digital supply voltage for the
core
digital supply voltage
VIH
VIL
VOH
VOL
IDDD33
IDDD18
Ptot
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
digital supply current for the
pads
digital supply current for the
core
total power dissipation
Ci
Tamb
input capacitance
ambient temperature
XTAL; pin XIN
VIH HIGH-level input voltage
VIL LOW-level input voltage
PLL
VDDD(PLL)
VDDA(PLL)
digital PLL supply voltage
analog PLL supply voltage
ADC
VDDA1
VDDA2,VDDA3
VIP,VIM
Vi
Vref(pos)
Vref(neg)
Voffset
Ri
Ci
B
analog ADC supply voltage
analog ADC supply voltage
analog ADC inputs
signal input range
positive reference voltage
negative reference voltage
input offset voltage
input resistance (VIP or VIM)
input capacitance (VIP or VIM)
input full power bandwidth
CONDITIONS
VDDD = 3.3 V ±10%
MIN.
2.97
VDDD = 1.8 V ±5%
1.7
only for 5 V
requirements; note 1
TTL input; note 2
TTL input
note 3
fs = 28.92 MHz;
symbol rate = 7 Mbaud
fs = 28.92 MHz;
symbol rate = 7 Mbaud
fs = 28.92 MHz;
symbol rate = 7 Mbaud
4.75
2
0
2.4
−
−
−
−
−
0
TYP.
3.3
1.8
5.0
−
−
−
−
46
120
540
−
−
0.7VDDD33
0
−
−
VDDD = 1.8 V ±5%
VDDA = 3.3 V ±10%
1.7
2.97
1.8
3.3
VDDA = 1.8 V ±5%
VDDA = 3.3 V ±10%
IR = VIP − VIM
3 dB bandwidth
1.7
2.97
−0.5
−0.5 to −1.0
1.95
0.95
−25
−
−
40
1.8
3.3
−
−
2.15
1.15
−
10
5
50
MAX.
3.63
1.9
5.25
VDDD50
0.8
−
0.4
−
−
−
5
70
UNIT
V
V
V
V
V
V
V
mA
mA
mW
pF
°C
VDDD33
0.3VDDD33
V
V
1.9 V
3.63 V
1.9 V
3.63 V
VDDA3 + 0.5 V
+0.5 to +1.0 V
2.35 V
1.35 V
+25 mV
− kΩ
10 pF
− MHz
Notes
1. The voltage level of the 5 V supply must always exceed or at least equal the voltage level of the 3.3 V supply during
power-up and power-down in order to guarantee protection against latch-up.
2. All digital inputs are 5 V tolerant except pin XIN.
3. IOH, IOL = ±4 mA for pins SACLK, SCL, SDA, SDAT, SCLT, TCK, TDI, TRST, TMS, TDO, GPIO, UNCOR, PSYNC,
OCLK, DEN and DO[7:0]. For all other pins, IOH, IOL = ±2 mA.
2001 Oct 01
8
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
© Koninklijke Philips Electronics N.V. 2001
SCA73
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/04/pp16
Date of release: 2001 Oct 01
Document order number: 9397 750 08497
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页数 | 16 页 | ||
下载 | [ TDA10021HT.PDF 数据手册 ] |
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