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PDF ( 数据手册 , 数据表 ) 74HCT193

零件编号 74HCT193
描述 Presettable synchronous 4-bit binary up/down counter
制造商 Philips
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74HCT193 数据手册, 描述, 功能
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT193
Presettable synchronous 4-bit
binary up/down counter
Product specification
File under Integrated Circuits, IC06
December 1990







74HCT193 pdf, 数据表
Philips Semiconductors
Presettable synchronous 4-bit binary
up/down counter
Product specification
74HC/HCT193
Tamb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HC
+25
40 to +85
40 to +125
UNIT
VCC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
tW master reset pulse width 100 25 125 150 ns 2.0 Fig.10
HIGH
20 9 25 30
4.5
17 7 21 26
6.0
tW parallel load pulse width 100 19 125 150 ns 2.0 Fig.9
LOW
20 7 25 30
4.5
17 6 21 26
6.0
trem removal time
50 8 65 75 ns 2.0 Fig.9
PL to CPU, CPD
10 3
13
15
4.5
9 2 11 13
6.0
trem removal time
50 0 65 75 ns 2.0 Fig.10
MR to CPU, CPD
10 0
13
15
4.5
9 0 11 13
6.0
tsu set-up time
Dn to PL
80 22 100 120 ns 2.0 Fig.11 note:
16 8 20 24
14 6 17 20
4.5 CPU = CPD =
6.0 HIGH
th hold time
Dn to PL
0 14
0
0
ns 2.0 Fig.11
0 5
0
0
4.5
0 4
0
0
6.0
th hold time
CPU to CPD,
CPD to CPU
80 22 100 120 ns 2.0 Fig.13
16 8 20 24
4.5
8 6 17 20
6.0
fmax maximum up, down clock 4.0 13.5
3.2
2.6
MHz 2.0 Fig.7
pulse frequency
20 41
16
13
4.5
24 49
19
15
6.0
December 1990
8














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