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PDF ( 数据手册 , 数据表 ) ZVP3306A

零件编号 ZVP3306A
描述 P-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET
制造商 Zetex Semiconductors
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ZVP3306A 数据手册, 描述, 功能
P-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 60 Volt VDS
* RDS(on)=14
ZVP3306A
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at Tamb=25°C
Pulsed Drain Current
Gate Source Voltage
Power Dissipation at Tamb=25°C
Operating and Storage Temperature Range
SYMBOL
VDS
ID
IDM
VGS
Ptot
Tj:Tstg
D
G
S
E-Line
TO92 Compatible
VALUE
-60
-160
-1.6
± 20
625
-55 to +150
UNIT
V
mA
A
V
mW
°C
ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BVDSS -60
V ID=-1mA, VGS=0V
Gate-Source Threshold
Voltage
VGS(th) -1.5 -3.5 V
ID=-1mA, VDS= VGS
Gate-Body Leakage
IGSS
20 nA VGS=± 20V, VDS=0V
Zero Gate Voltage Drain
Current
IDSS
-0.5 µA
-50 µA
VDS=-60 V, VGS=0
VDS=-48 V, VGS=0V, T=125°C(2)
On-State Drain Current(1)
ID(on)
-400
mA VDS=-18 V, VGS=-10V
Static Drain-Source On-State RDS(on)
Resistance (1)
14
VGS=-10V,ID=-200mA
Forward Transconductance gfs
(1)(2)
60
mS VDS=-18V,ID=-200mA
Input Capacitance (2)
Common Source Output
Capacitance (2)
Ciss
Coss
50 pF
25 pF VDS=-18V, VGS=0V, f=1MHz
Reverse Transfer Crss 8 pF
Capacitance (2)
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
td(on)
tr
td(off)
tf
8 ns
8 ns VDD-18V, ID=-200mA
8 ns
8 ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle 2%
(2) Sample test.
3-429
Switching times measured with 50source impedance and <5ns rise time on a pulse generator
(
3
)












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