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PDF ( 数据手册 , 数据表 ) ZVN2110A

零件编号 ZVN2110A
描述 N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET
制造商 Zetex Semiconductors
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ZVN2110A 数据手册, 描述, 功能
N-CHANNEL ENHANCEMENT
MODE VERTICAL DMOS FET
ISSUE 2 – MARCH 94
FEATURES
* 100 Volt VDS
* RDS(on)= 4
ZVN2110A
ABSOLUTE MAXIMUM RATINGS.
PARAMETER
Drain-Source Voltage
Continuous Drain Current at Tamb=25°C
Pulsed Drain Current
Gate Source Voltage
Power Dissipation at Tamb=25°C
Operating and Storage Temperature Range
SYMBOL
VDS
ID
IDM
VGS
Ptot
Tj:Tstg
D
G
S
E-Line
TO92 Compatible
VALUE
100
320
6
± 20
700
-55 to +150
UNIT
V
mA
A
V
mW
°C
ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).
PARAMETER
SYMBOL MIN. MAX. UNIT CONDITIONS.
Drain-Source Breakdown
Voltage
BVDSS 100
V ID=1mA, VGS=0V
Gate-Source Threshold
Voltage
VGS(th)
0.8
2.4
V
ID=1mA, VDS= VGS
Gate-Body Leakage
Zero Gate Voltage Drain
Current
IGSS
IDSS
On-State Drain Current(1)
Static Drain-Source On-State
Resistance (1)
ID(on)
RDS(on)
1.5
20 nA VGS=± 20V, VDS=0V
1 µA VDS=100V, VGS=0
100 µA VDS=80V, VGS=0V, T=125°C(2)
A VDS=25V, VGS=10V
4 VGS=10V,ID=1A
Forward Transconductance gfs
(1)(2)
250
mS VDS=25V,ID=1A
Input Capacitance (2)
Common Source Output
Capacitance (2)
Ciss
Coss
75 pF
25 pF VDS=25 V, VGS=0V, f=1MHz
Reverse Transfer Crss 8 pF
Capacitance (2)
Turn-On Delay Time (2)(3)
Rise Time (2)(3)
Turn-Off Delay Time (2)(3)
Fall Time (2)(3)
td(on)
tr
td(off)
tf
7 ns
8 ns VDD 25V, ID=1A
13 ns
13 ns
(1) Measured under pulsed conditions. Width=300µs. Duty cycle 2%
(2) Sample test.
Switching times measured with 50source impedance and <5ns rise time on a pulse generator
3
)












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