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PDF ( 数据手册 , 数据表 ) X1288

零件编号 X1288
描述 2-Wire RTC Real Time Clock/Calendar/CPU Supervisor with EEPROM
制造商 Xicor
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X1288 数据手册, 描述, 功能
Preliminary Information
New Features
Repetitive Alarms &
Temperature Compensation
2-WireRTC Real Time Clock/Calendar/CPU Supervisor with EEPROM
X1288
FEATURES
• Real Time Clock/Calendar
— Tracks time in Hours, Minutes, Seconds and Hun-
dredths of a Second
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
— Internal feedback resistor and compensation
capacitors
— 64 position Digitally Controlled Trim Capacitor
— 6 digital-frequency adjustment setting to ±30ppm
• CPU Supervisor Functions
— Power On Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 32K x 8 Bits of EEPROM
— 128-Byte Page Write Mode
— 8 modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
—Data Retention: 100 years
—Endurance: 100,000 cycles per byte
• 2-Wire™ Interface interoperable with I2C*
— 400kHz data transfer rate
• Frequency Output (SW Selectable: Off, 1Hz, 100Hz,
or 32.768kHz)
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 16-Lead SOIC and 14-Lead TSSOP
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio / Video Components
• Set Top Box / Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers / PDA
• POS Equipment
• Test Meters / Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial / Medical / Automotive
BLOCK DIAGRAM
32.768kHz
X1
X2
PHZ/IRQ
Select
SCL
SDA
Serial
Interface
Decoder
RESET
Control
Decode
Logic
8
OSC
Compensation
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Watchdog
Timer
Low Voltage
Reset
Time
Keeping
Registers
(SRAM)
Compare
Alarm Regs
(EEPROM)
256K
EEPROM
ARRAY
Battery
Switch
Circuitry
VCC
VBACK
*I2C is a Trademark of Philips.
REV 1.1.30 3/24/04
www.xicor.com
1 of 31







X1288 pdf, 数据表
Preliminary Information
X1288
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
Stop
Condition
tWC
Start
Condition
Power Up Timing
Symbol
Parameter
Min.
Typ.(2)
Max.
Units
tPUR(1)
tPUW(1)
Time from Power Up to Read
Time from Power Up to Write
1 ms
5 ms
Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100%
tested. VCC slew rate should be between 0.2mV/µsec and 50mV/µsec.
(2) Typical values are for TA = 25°C and VCC = 5.0V
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
tWC(1)
Write Cycle Time
5 10 ms
Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS
Watchdog/Low Voltage Reset Parameters (See Figures 3 and 4)
Symbols
VPTRIP
tRPD
tPURST
Parameters
Programmed Reset Trip Voltage
X1288-4.5A
X1288
X1288-2.7A
X1288-2.7
VCC Detect to RESET LOW
Power Up Reset Time-out Delay
Min.
4.50
4.25
2.75
2.55
100
Typ.
4.63
4.38
2.85
2.65
250
Max.
4.75
4.50
2.95
2.75
500
400
Unit
V
ns
ms
tF
tR
tWDO
tRST
tRSP
VRVALID
VCC Fall Time
VCC Rise Time
Watchdog Timer Period (Crystal=32.768kHz):
WD1=0, WD0=0, (default)
WD1=0, WD0=1
WD1=1, WD0=0
Watchdog Reset Time-out Delay (Crystal=32.768kHz)
2-Wire interface
Reset Valid VCC
10
10
1.7 1.75
725 750
225 250
225 250
1
1.0
1.8
775
275
275
µs
µs
s
ms
ms
ms
µs
V
REV 1.1.30 3/24/04
www.xicor.com
8 of 31







X1288 equivalent, schematic
Preliminary Information
X1288
Table 6. Digital Trimming Registers
DTR Register
DTR2 DTR1 DTR0
000
010
001
011
100
110
101
111
Estimated frequency
PPM
0
+10
+20
+30
0
-10
-20
-30
Analog Trimming Register (ATR) (Non-volatile)
Six analog trimming Bits from ATR5 to ATR0 are pro-
vided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capacitance
adjustment. Using a Citizen CFS-206 crystal with differ-
ent ATR bit combinations provides an estimated ppm
range from +116ppm to -37ppm to the nominal frequency
compensation. The combination of digital and analog
trimming can give up to +146ppm adjustment.
The on-chip capacitance can be calculated as follows:
CATR = [(ATR value, decimal) x 0.25pF] + 11.0pF
Note that the ATR values are in two’s complement, with
ATR(000000) = 11.0pF, so the entire range runs from
3.25pF to 18.75pF in 0.25pF steps.
The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi-
mately 2pF of package and board capacitance in addi-
tion to the ATR value.
See Application section and Xicor’s Application Note
AN154 for more information.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/
control register requires the following steps:
– Write a 02h to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
– Write a 06h to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write cycle,
so the sequence must be repeated to again initiate
another change to the CCR contents. If the
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
POWER ON RESET
Application of power to the X1288 activates a Power
On Reset Circuit that pulls the RESET pin active. This
signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When VCC exceeds the device VTRIP threshold value
for typically, 250ms the circuit releases RESET, allow-
ing the system to begin operation. Recommended VCC
slew rate is between 0.2V/ms and 50V/ms.
WATCHDOG TIMER OPERATION
The watchdog timer is selectable. By writing a value to
WD1 and WD0, the watchdog timer can be set to 3 dif-
ferent time out periods or off. When the Watchdog
timer is set to off, the watchdog circuit is configured for
low power operation.
REV 1.1.30 3/24/04
www.xicor.com
16 of 31










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