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PDF ( 数据手册 , 数据表 ) X1286

零件编号 X1286
描述 Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
制造商 Intersil Corporation
LOGO Intersil Corporation LOGO 


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X1286 数据手册, 描述, 功能
New Features
Repetitive Alarms &
Temperature Compensation
2-Wire™ RTC, 256K (32K x 8)
®
Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
FEATURES
• Real Time Clock/Calendar
— Tracks time in Hours, Minutes, Seconds and Hun-
dredths of a Second
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
— Internal feedback resistor and compensation
capacitors
— 64 position Digitally Controlled Trim Capacitor
— 6 digital frequency adjustment settings to
±30ppm
• Battery Switch or Super Cap Input
• 32K x 8 Bits of EEPROM
— 128-Byte Page Write Mode
— 8 modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
— Data Retention: 100 years
— Endurance: 100,000 cycles per byte
• 2-Wire™ Interface interoperable with I2C*
— 400kHz data transfer rate
• Frequency Output (SW Selectable: Off, 1Hz, 100Hz,
or 32.768kHz)
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 8-Lead EIAJ SOIC and 14-Lead TSSOP
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio / Video Components
• Set Top Box / Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers / PDA
• POS Equipment
• Test Meters / Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial / Medical / Automotive
BLOCK DIAGRAM
32.768kHz
X1
X2
PHZ/IRQ
Select
SCL
SDA
Serial
Interface
Decoder
Control
Decode
Logic
8
OSC
Compensation
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Time
Keeping
Registers
(SRAM)
Compare
Alarm Regs
(EEPROM)
256K
EEPROM
ARRAY
*I2C is a Trademark of Philips.
REV 1.1 7/8/04
www.intersil.com
Battery
Switch
Circuitry
VCC
VBACK
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X1286 pdf, 数据表
X1286
DESCRIPTION
The X1286 device is a Real Time Clock with clock/
calendar, two polled alarms with integrated 32kx8
EEPROM, oscillator compensation, and battery backup
switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving board
area and component cost.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds and 1/100 of a
second. The Calendar has separate registers for Date,
Month, Year and Day-of-week. The calendar is correct
through 2099, with automatic leap year correction.
The powerful Dual Alarms can be set to any Clock/
Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
The PHZ/IRQ pin may be software selected to provide
a frequency output of 1 Hz, 100 Hz, or 32,768 Hz.
The device offers a backup power input pin. This
VBACK pin allows the device to be backed up by battery
or SuperCap. The entire X1286 device is fully
operational from 2.7 to 5.5 volts and the clock/calendar
portion of the X1286 device remains fully operational
down to 1.8 volts (Standby Mode).
The X1286 device provides 256K bits of EEPROM with
8 modes of BlockLock™ control. The BlockLock allows
a safe, secure memory for critical user and
configuration data, while allowing a large user storage
area.
PIN DESCRIPTIONS
X1286
8-pin EIAJ SOIC
14- pin TSSOP
X1
X2
PHZ/IRQ
VSS
1
2
3
4
8 VCC
7 VBACK
6 SCL
5 SDA
X1 1
X2 2
NC 3
NC 4
NC 5
PHZ/IRQ 6
VSS 7
14 VCC
13 VBACK
12 NC
11 NC
10 NC
9 SCL
8 SDA
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speed.
VBACK
This input provides a backup supply voltage to the
device. VBACK supplies power to the device in the
event the VCC supply fails. This pin can be connected
to a battery, a Supercap or tied to ground if not used.
Programmable Frequency/Interrupt Output – PHZ/IRQ
This is either an output from the internal oscillator or an
interrupt signal output. It is a CMOS output.
When used as frequency output, this signal has a fre-
quency of 32.768kHz, 100Hz, 1Hz or inactive.
When used as interrupt output, this signal notifies a
host processor that an alarm has occurred and an
action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and
are found in address 0011h of the Clock Control Mem-
ory map. See “Programmable Frequency Output Bits—
FO1, FO0” on page 13.
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1286 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.
REV 1.1 7/8/04
www.intersil.com
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X1286 equivalent, schematic
X1286
Figure 7. Slave Address, Word Address, and Data Bytes (128 Byte pages)
Device Identifier
Array
CCR
1
1
0
1
1
0
0
1
11
Slave Address Byte
1 R/W Byte 0
0 A14 A13 A12 A11 A10 A9
Word Address 1
A8 Byte 1
Word Address 0
A7 A6 A5 A4 A3 A2 A1 A0 Byte 2
Data Byte
D7 D6 D5 D4 D3 D2 D1 D0
Byte 3
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the oper-
ation to be performed. When this R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 7.
After loading the entire Slave Address Byte from the
SDA bus, the X1286 compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0h, so
a current address read of the EEPROM array starts at
address 0. When required, as part of a random read,
the master must supply the 2 Word Address Bytes as
shown in Figure 7.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. That is if the random read is from the
array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the Clock/
Control Registers, the slave byte must be 1101111x in
both places.
Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
receipt of each address byte, the X1286 responds with
an acknowledge. After receiving both address bytes
the X1286 awaits the eight bits of data. After receiving
the 8 data bits, the X1286 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1286 then begins
an internal write cycle of the data to the nonvolatile
memory. During the internal write cycle, the device
inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance. See Figure 8.
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the write
command, the X1286 will not initiate an internal write
cycle, and will continue to ACK commands.
Page Write
The X1286 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit up to 127
REV 1.1 7/8/04
www.intersil.com
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