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PDF ( 数据手册 , 数据表 ) X1243V8

零件编号 X1243V8
描述 Real Time Clock/Calendar/Alarm with EEPROM
制造商 Xicor
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X1243V8 数据手册, 描述, 功能
16K
X1243
2-WireRTC
Real Time Clock/Calendar/Alarm with EEPROM
FEATURES
• 2 Alarms—Interrupt Output
—Settable on the Second, 10s of Seconds,
Minute, 10s of Minutes, Hour, Day, Month, or
Day of the Week
—Repeat alarm for time base generation
• 2 Wire Interface interoperable with I2C.
—400kHz data transfer rate
• Secondary Power Supply Input with internal
switch-over circuitry.
• Year 2000 Compliant
• 2K bytes of EEPROM
—64 Byte Page Write Mode
—3 bit Block Lock
• Low Power CMOS
—<1µA Operating Current
—<3mA Active Current during Program
—<400µA Active Current during Data Read
• Single Byte Write Capability
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
—8-Lead SOIC Package, 8L TSSOP Package
DESCRIPTION
The X1243 is a Real Time Clock with clock/calendar
circuits and two alarms. The dual port clock and alarm
registers allow the clock to operate, without loss of
accuracy, even during read and write operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
An alarm match of the RTC sets an interrupt flag and
activates an interrupt pin. An alternative alarm function
provides a pulsed interrupt for long time constant time-
bases.
The device offers a backup power input pin. This
Vback pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational
from 1.8 to 5.5 volts.
The X1243 provides a 2K byte EEPROM array, giving
a safe, secure memory for critical user and configura-
tion data. This memory is unaffected by complete fail-
ure of the main and backup supplies.
BLOCK DIAGRAM
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
Serial
Interface
Decoder
IRQ
Control
Decode
Logic
8
Control
Registers
(EEPROM)
Status
Register
(SRAM)
Interrupt Enable
Alarm
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
9900-3003.1 4/1/99
1
Alarm
Compare
Alarm Regs
(EEPROM)
16K
EEPROM
Array
Characteristics subject to change without notice







X1243V8 pdf, 数据表
X1243
SCL from Master
Data Output from
Transmitter
Data Output
from Receiver
1
89
Start
Acknowledge
Figure 5. Acknowledge Response From Receiver
Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 5.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
—The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
—All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
—The 2nd Data Byte of a Register Write Operation
(when only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
WRITE OPERATIONS
Byte Write
For a byte write operation, the device requires the
Slave Address Byte and the Word Address Bytes. This
gives the master access to any one of the words in the
array or CCR. (Note: Prior to writing to the CCR, the
master must write a 02h, then 06h to the status regis-
ter in preceding operations to enable the write opera-
tion. See “Writing to the Clock/Control Registers” on
page 6.) Upon receipt of each address byte, the
X1243 responds with an acknowledge. After receiving
both address bytes the X1243 awaits the eight bits of
data. After receiving the 8 data bits, the X1243 again
responds with an acknowledge. The master then ter-
minates the transfer by generating a stop condition.
The X1243 then begins an internal write cycle of the
data to the nonvolatile memory. During the internal
write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 6.
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X1243 will not initiate an internal
write cycle, and will continue to ACK commands.
8







X1243V8 equivalent, schematic
X1243
AC Specifications - TA = -40˚C to +85˚C, VCC = +2.7V to +5.5V, unless otherwise specified.
Symbol
fSCL
tIN(1)
tAA
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
tR(1)
tF(1)
Cb
Parameter
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission
can start
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive load for each bus line
400kHz Option
Min Max
0 400
50
0.1 0.9
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb(2)
20 +.1Cb(2)
300
300
400
Units
KHz
nS
µS
µS
µS
µS
µS
µS
nS
µS
µS
nS
nS
nS
pF
1. This parameter is periodically sampled and not 100% tested.
2. Cb = total capacitance of one bus line in pF.
Timing Diagrams
Bus Timing
SCL
tSU:STA
SDA IN
SDA OUT
tF
tHIGH tLOW
tR
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
16










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