DataSheet8.cn


PDF ( 数据手册 , 数据表 ) X1240

零件编号 X1240
描述 Real Time Clock/Calendar with EEPROM
制造商 Xicor
LOGO Xicor LOGO 


1 Page

No Preview Available !

X1240 数据手册, 描述, 功能
Preliminary Information
16K
X1240
2-Wire RTC
Real Time Clock/Calendar with EEPROM
FEATURES
• 2-Wire Interface interoperable with I2C.
—400kHz data transfer rate
• Secondary Power Supply Input with internal
switch-over circuitry.
• Year 2000 Compliant
• 2K bytes of EEPROM
—64 Byte Page Write Mode
—3 bit Block Lock
• Low Power CMOS
—<1µA Operating Current
—<3mA Active Current during Program
—<400µA Active Current during Data Read
• Single Byte Write Capability
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—1,000,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
—8-Lead SOIC Package, 8L TSSOP Package
DESCRIPTION
The X1240 is a Real Time Clock with clock/calendar
circuits. The dual port clock register allows the clock to
operate, without loss of accuracy, even during read and
write operations.
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
The device offers a backup power input pin. This
Vback pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational
from 1.8 to 5.5 volts.
The X1240 provides a 2K byte EEPROM array, giving
a safe, secure memory for critical user and configura-
tion data. This memory is unaffected by complete fail-
ure of the main and backup supplies.
BLOCK DIAGRAM
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
Serial
Interface
Decoder
Control
Decode
Logic
8
Control
Registers
(EEPROM)
Status
Register
(SRAM)
16K
EEPROM
Array
©Xicor, Inc. 1994, 1995, 1996, 1997, 1998, 1999 Patents Pending
9900-3003.5 12/6/99 CM
1
Characteristics subject to change without notice







X1240 pdf, 数据表
X1240
Figure 6. Byte Write Sequence
Signals from
the Master
S
t
a
r
t
Slave
Address
Word
Address 1
Word
Address 0
SDA Bus
Signals from
the Slave
1 111 0 00000
AA
CC
KK
A
C
K
Data
S
t
o
p
A
C
K
Figure 7. Writing 30 bytes to a 64-byte page starting at adress 40.
7 bytes
address
=6
address pointer
ends here
Addr = 7
address
40
23 bytes
address
63
Figure 8. Page Write Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a Slave
r
t
Address
Word
Address 1
Word
Address 0
(1 < n < 64)
Data
(1)
Data
(n)
1 1 1 10 0 00 00
AA
CC
KK
A
C
K
S
t
o
p
A
C
K
Page Write
The X1240 has a page write operation. It is initiated in
the same manner as the byte write operation; but instead
of terminating the write cycle after the first data byte is
transferred, the master can transmit up to 63 more bytes
to the memory array and up to 7 more bytes to the
clock/control registers. (Note: Prior to writing to the
CCR, the master must write a 02h, then 06h to the sta-
tus register in two preceding operations to enable the
write operation. See “Writing to the Clock/Control Reg-
isters” on page 5.)
After the receipt of each byte, the X1240 responds
with an acknowledge, and the address is internally
incremented by one. When the counter reaches the
end of the page, it “rolls over” and goes back to the
first address on the same page. This means that the
master can write 64 bytes to a memory array page or 8
bytes to a CCR section starting at any location on that
page. If the master begins writing at location 40 of the
memory and loads 30 bytes, then the first 23 bytes are
written to addresses 40 through 63, and the last 7
bytes are written to columns 0 through 6. Afterwards,
8







X1240 equivalent, schematic
X1240
Write Cycle Timing
SCL
SDA
8th bit of last byte
ACK
Stop
Condition
tWC
Start
Condition
Power Up Timing
Symbol
tPUR(1)
tPUW(1)
Parameter
Time from Power Up to Read
Time from Power Up to Write
Min.
Typ(1)
Max.
1
5
Units
mS
mS
Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically
sampled and not 100% tested.
(2) Typical values are for TA = 25˚C and VCC = 5.0V
Nonvolatile Write Cycle Timing
Symbol
tWC(1)
Parameter
Write Cycle Time
Min.
Typ.(1)
5
Max.
10
Units
mS
Notes: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
16










页数 19 页
下载[ X1240.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
X1240Real Time Clock/Calendar with EEPROMXicor
Xicor
X1240S8Real Time Clock/Calendar with EEPROMXicor
Xicor
X1240S8IReal Time Clock/Calendar with EEPROMXicor
Xicor
X1240V8Real Time Clock/Calendar with EEPROMXicor
Xicor

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap