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PDF ( 数据手册 , 数据表 ) WT8048N3

零件编号 WT8048N3
描述 DPMS (Display Power Management Signaling) Detector for Green Monitor
制造商 ETC
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WT8048N3 数据手册, 描述, 功能
eltrend
WT8048
DPMS (Display Power Management
Signaling) Detector for Green Monitor
Aug. 31, 1995
DESCRIPTION
The WT8048 is a 8 pin P-DIP package IC, designed for the application of Power Saving
Monitor or Green Monitor.
As per DPMS proposal, the WT8048 provides a detective circuit of monitor power
management for the convenience of designers in designing Power Saving Monitor.
FEATURES
{ Accepting two seperated H&V synchronous signals with positive/ negative polarity.
{ Capable of processing horizontal frequency between 0Hz to 100kHz, and vertical
frequency between 0Hz to 100Hz.
{ Power Saving mode - It can detect the conditions of monitor to decide which will be
selected as following: ON mode / STAND_BY mode / SUSPEND mode / OFF mode.
{ An Override mode is defined to override the DPMS function during the design, test,
burn-in manufacture or diagnostic process if desired.
APPLICATION
{ DPMS mode's detection for Green Monitor
Weltrend Semiconductor, Inc.
2F., No. 24, Ind. E. 9th Rd., Science-Based Ind. Park,
Hsin-Chu, Taiwan, R. O. C.
Tel: 886-35-780241 Fax: 886-35-7704191







WT8048N3 pdf, 数据表
eltrend
WT8048
Synchronization Signals
The basis of DPMS standard is the condition of the synchronization signals to the display.
Two conditions are defined: pulses and no pulses.
{ PULSES
pulses for the Horizontal Sync. Signal are defined as greater than 10KHz repetition
frequency and pulses for the Vertical Sync. Signal are defiened as greater than 40Hz
repetition frequency.
{ NO PULSES
No pulses is defined as less than 10Hz repetition frequency with less than 25% duty cycle
Please refer to the Fig. 1 for the way WT8048 Implement pulses/ no pulses state, between
10Hz and 15KHz / 10KHz, 10Hz and 40Hz. WT8048 use hystersis technique to stable state in
between.
STATE
P
NP
10 Hz
fT
H_SYNC
FREQUENCY
f = 15k for WT8048
T
= 10k for WT8048N1/N2/N3/N4
STATE
P
NP
10 Hz
40 Hz
V_SYNC
FREQUENCY
Figure 1: pulses / no pulses state implementation
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