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PDF ( 数据手册 , 数据表 ) WM8144

零件编号 WM8144
描述 Integrated 10-bit Data Acquisition system for Imaging Applications
制造商 Wolfson Microelectronics plc
LOGO Wolfson Microelectronics plc LOGO 


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WM8144 数据手册, 描述, 功能
WM8144-10
Production Data
October 1997 Rev. 3.0
Integrated 10-bit Data Acquisition system for
Imaging Applications
Description
Features
WM8144-10 integrates the analogue signal conditioning
required by CCD sensors with a 10-bit ADC and optional
pixel-by-pixel image compensation. WM8144-10 requires
minimal external circuitry and provides a cost effective
sensor-to-digital domain system solution.
Each analogue conditioning channel provides reset level
clamp, CDS, fine offset level shifting and gain
amplification. The three channels are multiplexed into the
ADC. Output from the ADC can either be direct or passed
through a digital post-processing function. The post-
processing provides compensation for variations in offset
and shading on a pixel-by-pixel basis.
• Reset level clamp
• Correlated Double Sampling (CDS)
• Fine offset level shifting
• Programmable Gain Amplification
• 10-Bit ADC with maximum 6 MSPS
• Digital post-processing for pixel-by-pixel
image compensation
• Simple clocking scheme
• Control by serial or parallel interface
• Time-multiplexed eight-bit data output mode
• 48 pin TQFP package
• Pin compatible with WM8144-12
The flexible output architecture allows ten-bit data to be
accessed either on a ten-bit bus or via a time-multiplexed
eight-bit bus. The WM8144-10 can be configured for pixel-
by-pixel or line-by-line multiplexing operation. Reset level
clamp and/or CDS features can be optionally bypassed.
Device configuration is either by a simple serial or eight-
bit parallel interface.
Applications
• Document scanners
• CCD sensor interfaces
• Contact image sensor (CIS) interfaces
Block Diagram
VRLC
VRU VRT
VRB VRL
VMID
VSMP MCLK RLC
AVDD AGND DVDD1 DVDD2 DGND
VMID
RINP
GINP
BINP
MUX
CL RS VS
S/H
S/H
PGA
CDS
5-BIT REG
S/H
S/H
PGA
CDS
5-BIT REG
S/H
S/H
PGA
CDS
5-BIT REG
TIMING CONTROL
OFFSET
8-BIT + SIGN
DAC
VMID
OFFSET
8-BIT + SIGN
DAC
VMID
OFFSET
8-BIT + SIGN
DAC
VMID
WM8144-10
EXTERNAL
DATA STORE
INTERFACE
M
U
X
10 BIT
ADC
IMAGE
COMPENSATION
PROCESSING
10/8
MUX
CONFIGURABLE
SERIAL/PARALLEL
CONTROL INTERFACE
CC[2:0]
DV
CDATA(7:0)
ORNG
OEB
OP[9:0]
PNS
SDI / DNA
SCK / RNW
SEN / STB
NRESET
Production Data data sheets contain fi-
nal specifications current on publication
date. Supply of products conforms to
Wolfson Microelectronics standard terms
and conditions
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK
Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176
www: http://www.wolfson.co.uk
© 1997 Wolfson Microelectronics







WM8144 pdf, 数据表
WM8144-10
Typical Performance
VDD = 5V, GND = 0 V, ........TA = 25oC.
1
0. 8
0. 6
0. 4
0. 2
0
-0.2
-0.4
-0.6
-0.8
-1
0
WM8144 10 Bit DNL Plot
256 512 768
AADDCCCoCdeode
ADC 10 Bit DNL
1024
PGA Gain
8
Red
7 Gr een
6 Blue
5
4
3
2
1
0
0 1 2 34 5 6 7 8
MCLK = 12.3MHz. Input sPetGtoA2.5GV a+/i-n10C0moVd.eOther 2 are at 2.5VGaCinolo
PGA Gain Code vs. Actual Gain
@ MCLK = 12.3MHz
Gai n DNL
5
4 Red
3 Gr een
2 Blue
1
0
-1
-2
-3
-4
-5
01
MCLK = 12.3MHz.
In2puPt 2G.53VA+G/- 1a04i0nmVC. oO5dt heer
2
6
are
at
7
2.5V.
8
CoGloauinr. Vd
PGA DNL @ MCLK = 12.3MHz
WM8144 10 Bit INL Plot
5
4
3
2
1
0
-1
-2
-3
-4
-5
0 256 512 768 1024
ADADCC CCodeode
ADC 10 Bit INL
PGA Gain
8
Red
7 Gr een
6 Blue
5
4
3
2
1
0
0123 45678
MCLK = 8MHz.
Input set
tPo G2.5AV +G/-a10in0mCV.oOdtheer 2 are at
2. 5V
Colour.
Gain
PGA Gain Code vs. Actual Gain
@ MCLK = 8MGaHin zDNL
5
4 Red
3 Gr een
2 Blue
1
0
-1
-2
-3
-4
-5
012345678
MCLK = 8MHz. Input 2.P5VG+A/ - 1G00amVin. OCthoedr 2eare at 2.5V. ColouGr.aVindd =
PGA DNL @ MCLK = 8MHz
Wolfson Microelectronics
8







WM8144 equivalent, schematic
WM8144-10
Operational Modes (Contd.)
Table 5: WM8144-10 Mode Summary
Wolfson Microelectronics
16










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