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PDF ( 数据手册 , 数据表 ) WM2619

零件编号 WM2619
描述 12-bit Parallel Input Voltage Output DAC
制造商 Wolfson Microelectronics plc
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WM2619 数据手册, 描述, 功能
WM2619
12-bit Parallel Input Voltage Output DAC
Production Data, June 1999, Rev 1.0
FEATURES
12-bit voltage output DAC
Single supply 2.7V to 5.5V operation
DNL ±0.4 LSB, INL ±1.5 LSB
Settling time 1µs typical
Low power consumption
- 8mW typical in slow mode - 5V supply
- 4.3mW typical in fast mode - 3V supply
Power down mode
APPLICATIONS
Battery powered test instruments
Digital offset and gain adjustment
Battery operated/remote industrial controls
Machine and motion control devices
Wireless telephone and communication systems
Speech synthesis
Arbitrary waveform generation
DESCRIPTION
The WM2619 is a 12-bit voltage output, resistor string, digital-to-
analogue converter. A hardware controlled power down mode is
provided that reduces power consumption to 50nW. In normal
operation the device dissipates 8mW at 5V or 4.3mW at 3V.
The device has been designed to interface efficiently to industry
standard microprocessors and DSPs.
Excellent performance is delivered with a typical DNL of 0.4 LSBs
and a settling time of 1µs. The output stage is buffered by a x2
gain near rail-to-rail amplifier, which features a Class A output
stage. The 12 data bits are double-buffered enabling the output to
be asynchronously updated under hardware control.
The device is available in a 20-pin TSSOP package. Commercial
temperature (0° to 70°C) and Industrial temperature (-40° to 85°C)
variants are supported.
ORDERING INFORMATION
DEVICE
WM2619CDT
WM2619IDT
TEMP. RANGE
0° to 70°C
-40° to 85°C
PACKAGE
20-pin TSSOP
20-pin TSSOP
BLOCK DIAGRAM
REFIN(12)
D[0-11]
(19,20, 1-10)
NWE (17)
NCS (18)
12-BIT
INPUT
REGISTER
data
REFERENCE
INPUT BUFFER
X1
12-BIT
DAC
LATCH
VDD
(11)
DAC
OUTPUT
BUFFER
X2
(13) OUT
POWER-ON
RESET
(14)
GND
(16)
NLDAC
POWERDOWN
CONTROL
(15)
NPD
WM2619
TYPICAL PERFORMANCE
1
VDD = 5V, VREF = 2.048V, Load = 10k/100pF
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
512
1024
1536
2048
2559
DIGITAL CODE
3071
3583
4095
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
http://www.wolfson.co.uk
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics’ Terms and conditions.
Masterrev1.0a.doc June 17, 1999 10:52
©1999 Wolfson Microelectronics Ltd.







WM2619 pdf, 数据表
WM2619
DEVICE DESCRIPTION
Production Data
GENERAL FUNCTION
The device uses a resistor string network buffered with an op amp to convert 12-bit digital data to
analogue voltage levels (see Block Diagram). The output voltage is determined by the reference
input voltage and the input code according to the following relationship:
Output voltage =
( ) CODE
2 VREF
4096
INPUT
OUTPUT
1111
1111
1111
( )2 VREF 4095
4096
::
1000
0000
0001
( ) 2049
2 VREF
4096
1000
0000
0000
( )2 VREF 2048 = VREF
4096
0111
1111
1111
( ) 2047
2 VREF
4096
::
0000
0000
0001
( )1
2 VREF
4096
0000
0000
0000
0V
Table 1 Binary Code Table (0V to 2VREFIN Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a
2kload with a 100pF load capacitance.
EXTERNAL REFERENCE
The reference voltage input is buffered which makes the DAC input resistance independent of
code. The REFIN pin has an input resistance of 10Mand an input capacitance of typically 5pF.
The reference voltage determines the DAC full-scale output.
HARDWARE CONFIGURATION OPTIONS
The WM2619 has two configuration options that are controlled by device pins.
DEVICE POWERDOWN
The device can be powered-down by pulling pin NPD (pin 15) high. This powers down the DAC.
This will reduce power consumption significantly. When the power down function is released the
device reverts to the DAC code set prior to power down.
DAC UPDATE
The NLDAC pin (Pin 16) can be held high to prevent serial word writes from updating the DAC
latch. By writing the new value to the DAC then pulling NLDAC low, the new DAC code is loaded
into the DAC latch.
PARALLEL INTERFACE
The device registers data on the positive edge of NWE (Pin 17). It must be enabled with NCS
(Pin 18) low.
WOLFSON MICROELECTRONICS LTD
Production Data Rev 1.0 June 1999
8














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