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PDF ( 数据手册 , 数据表 ) WEDPNF8M721V-1215BC

零件编号 WEDPNF8M721V-1215BC
描述 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
制造商 ETC
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WEDPNF8M721V-1215BC 数据手册, 描述, 功能
White Electronic Designs WEDPNF8M721V-XBX
8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module
Multi-Chip Package ADVANCED*
FEATURES
n Sector Architecture
n Package:
• 275 Plastic Ball Grid Array (PBGA), 32mm x 25mm
n Commercial, Industrial and Military Temperature Ranges
n Weight:
• WEDPNF8M721V-XBX - 2.5 grams typical
• One 16KByte, two 8KBytes, one 32KByte, and fif
teen 64KBytes in byte mode
• One 8K word, two 4K words, one 16K word, and
fifteen 32K word sectors in word mode.
• Any combination of sectors can be concurrently
erased. Also supports full chip erase
SDRAM PERFORMANCE FEATURES
n Organized as 8M x 72
n High Frequency = 100, 125MHz
n Single 3.3V ±0.3V power supply
n Fully Synchronous; all signals registered on positive
edge of system clock cycle
n Boot Code Sector Architecture (Bottom)
n Embedded Erase and Program Algorithms
n Erase Suspend/Resume
• Supports reading data from or programing data to a
sector not being erased
BENEFITS
n Internal pipelined operation; column address can be
changed every clock cycle
n Internal banks for hiding row access/precharge
n Programmable Burst length 1,2,4,8 or full page
n 4096 refresh cycles
FLASH PERFORMANCE FEATURES
n User Configurable as 1Mx8 or 512Kx16
n Access Times of 100, 120, 150ns
n 3.3 Volt for Read and Write Operations
n 1,000,000 Erase/Program Cycles
n 42% SPACE SAVINGS
n Reduced part count
n Reduced I/O count
• 14% I/O Reduction
n Suitable for hi-reliability applications
n SDRAM Upgradeable to 16M x 72 density (contact
factory for information)
n Flash upgradeable to 2M x 8 (or 1M x 16 or 512K x 32)
density
* This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
September 2002 Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com







WEDPNF8M721V-1215BC pdf, 数据表
White Electronic Designs WEDPNF8M721V-XBX
Accesses begin with the registration of an ACTIVE com-
mand which is then followed by a READ or WRITE com-
mand. The address bits registered coincident with the AC-
TIVE command are used to select the bank and row to be
accessed (BA0 and BA1 select the bank, A0-11 select the
row). The address bits (A0-8) registered coincident with
the READ or WRITE command are used to select the start-
ing column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information cover-
ing device initialization, register definition, command de-
scriptions and device operation.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those speci-
fied may result in undefined operation. Once power is ap-
plied to VDD and VDDQ (simultaneously) and the clock is
stable (stable clock is defined as a signal cycling within tim-
ing constraints specified for the clock pin), the SDRAM re-
quires a 100µs delay prior to issuing any command other
than a COMMAND INHIBIT or a NOP. Starting at some point
during this 100µs period and continuing at least through
the end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.
Once the 100µs delay has been satisfied with at least one
COMMAND INHIBIT or NOP command having been applied,
a PRECHARGE command should be applied. All banks must
be precharged, thereby placing the device in the all banks
idle state.
Once in the idle state, two AUTO REFRESH cycles must be
performed. After the AUTO REFRESH cycles are complete, the
SDRAM is ready for Mode Register programming. Because the
Mode Register will power up in an unknown state, it should
be loaded prior to applying any operational command.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the SDRAM. This definition includes the selec-
tion of a burst length, a burst type, a CAS latency, an oper-
ating mode and a write burst mode, as shown in Figure 3.
The Mode Register is programmed via the LOAD MODE REG-
ISTER command and will retain the stored information until
it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved), M4-
M6 specify the CAS latency, M7 and M8 specify the oper-
ating mode, M9 specifies the WRITE burst mode, and M10
and M11 are reserved for future use.
The Mode Register must be loaded when all banks are idle,
and the controller must wait the specified time before initi-
ating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown in Fig-
ure 3. The burst length determines the maximum number of
column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4 or 8 locations are
available for both the sequential and the interleaved burst
types, and a full-page burst is available for the sequential
type. The full-page burst is used in conjunction with the
BURST TERMINATE command to generate arbitrary burst
lengths.
Reserved states should not be used, as unknown opera-
tion or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of col-
umns equal to the burst length is effectively selected. All
accesses for that burst take place within this block, mean-
ing that the burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-8 when the
burst length is set to two; by A2-8 when the burst length is
set to four; and by A3-8 when the burst length is set to
eight. The remaining (least significant) address bit(s) is (are)
used to select the starting location within the block. Full-
page bursts wrap within the page if the boundary is reached.
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
CAS LATENCY
The CAS latency is the delay, in clock cycles, between the
registration of a READ command and the availability of the
first piece of output data. The latency can be set to two or
three clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
8







WEDPNF8M721V-1215BC equivalent, schematic
White Electronic Designs WEDPNF8M721V-XBX
TABLE 4 - DEVICE BUS OPERATIONS
Operation
Read
Write
Standby
Output Disable
Reset
Sector Protect (1)
FCS FOE
L
L
Vcc ±0.3V
L
X
L
L
H
X
H
X
H
Sector Unprotect (1)
LH
Temporary Sector Unprotect
X
X
FWE
RST Addresses (2)
FD0-7
H H FAIN FDOUT
L H FAIN FDOUT
X Vcc ± 0.3V
X
High Z
H H X High Z
X L X High Z
Sector Address,
L
VID FA6 = L, FA1 = H,
FDIN
FA0 = L
Sector Address,
L
VID FA6 = H, FA1 = H,
FDIN
FA0 = L
X VID
AIN
FDIN
F D8-15
BYTE1
BYTE1
= VIH
FDOUT
=VIL
FD8-14 = High Z
FDOUT
FD15 = FA-1
High Z
High Z
High Z
High Z
High Z
High Z
XX
XX
FDIN High Z
LEGEND:
L = Logic Low = VIL
X = Don’t Care
FDOUT = Flash Data Out
H = Logic High = VIH
FAIN = Flash Address In
VID = 12.0 ± 0.5V
FDIN = Flash Data In
NOTES:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector Protection/Unprotection" section.
2. Addresses are FA18: FA0 in word mode (BYTE1 = VIH), FA18: FA-1 in byte mode (BYTE1 = VIL)
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures
that not spurious alteration of the memory content occurs
during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor
read cycles that assert valid addresses on the device data
outputs. The device remains enabled for read access until
the command register contents are altered.
See “Reading Array Data” for more information. Refer to the
Flash AC Read-only Operations table for timing specifica-
tions and to Figure 11 for the timing diagram. IFCC1 in the
ICC Specifications and Conditions table represents the ac-
tive current specification for reading array data.
WRITE COMMANDS/COMMAND
SEQUENCES
To writes a command or command sequence (which in-
cludes programming data to the device and erasing sec-
tors of memory), the system must drive FWE and FCS to VIL,
and FOE to VIH.
For program operations, the BYTE1 pin determines whether
the device accepts program data in bytes or words. Refer
to “Word/Byte Configuration” for more information.
Bypass mode, only two write cycles are required to pro-
gram a byte, instead of four.
An erase operation can erase one sector, multiple sectors,
or the entire device. Table 5 indicates the address space
that each sector occupies. A “sector address” consists of
the address bits required to uniquely select a sector. The
“Flash Command Definitions” section has details on erasing
a sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on FD7-0. Standard read
cycle timings apply in this mode. Refer to the "Autoselect
Mode" and "Autoselect Command Sequence" sections for
more information.
IFCC2 in the DC Characteristics table represents the active
current specifications for the write mode. The “Flash AC
Characteristics” section contains timing specification tables
and timing diagrams for write operations.
PROGRAM AND ERASE OPERATION
STATUS
The device features an Unlock Bypass mode to facilitate
faster programming. Once the device enters the Unlock
During an erase or program operation, the system may check
the status of the operation by reading the status bits on FD7-
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
16










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