DataSheet8.cn


PDF ( 数据手册 , 数据表 ) W83194R-81

零件编号 W83194R-81
描述 100MHZ CLOCK FOR SIS CHIPSET
制造商 Winbond
LOGO Winbond LOGO 


1 Page

No Preview Available !

W83194R-81 数据手册, 描述, 功能
W83194R-81
100MHZ CLOCK FOR SIS CHIPSET
1.0 GENERAL DESCRIPTION
The W83194R-81 is a Clock Synthesizer for SiS chipset. W83194R-81 provides all clocks required
for high-speed RISC or CISC microprocessor such as AMD,Cyrix,Intel Pentium and also provides 16
different frequencies of CPU clocks frequency setting. All clocks are externally selectable with
smooth transitions. The W83194R-81 makes SDRAM in synchronous or asynchronous frequency
with CPU clocks.
The W83194R-81 provides I2C serial bus interface to program the registers to enable or disable each
clock outputs and W83194R-81 provides the 0.25%, 0.5% center type spread spectrum to reduce
EMI.
The W83194R-81 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30
pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as
maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide
better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
Supports Pentium, PentiumPro, AMD and Cyrix CPUs with I2C.
3 CPU clocks
13 SDRAM clocks for 3 DIMMs
6 PCI synchronous clocks.
Optional single or mixed supply:
(Vdd = Vddq4=Vddq3 = Vddq2b = 3.3V, Vddq2=2.5V) or
(Vdd = Vddq4=Vddq3 = 3.3V, Vddq2=Vdq2b = 2.5V)
Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns
SDRAM frequency synchronous or asynchronous to CPU clocks
Smooth frequency switch with selections from 66 to 133mhz(including 90MHz)
I2C 2-Wire serial interface and I2C read back
0.25%, 0.5% center type spread spectrum to reduce EMI
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
MODE pin for power Management
48 MHz for USB
24 MHz for super I/O
48-pin SSOP package
Publication Release Date: Dec. 1998
- 1 - Revision 0.20







W83194R-81 pdf, 数据表
W83194R-81
8.2 2-WIRE I2C CONTROL INTERFACE
PRELIMINARY
The clock generator is a slave I2C component which can be read back the data stored in the latches
for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-wire
control interface allows each clock output individually enabled or disabled. On power up, the
W83194R-81 initializes with default register settings, and then it optional to use the 2-wire control
interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a start condition followed by 7-bit slave address [1101 0010], command code
checking [0000 0000], and byte count checking. After successful reception of each byte, an
acknowledge (low) on the SDATA wire will be generated by the clock chip. Controller can start to
write to internal I2C registers after the string of data. The sequence order is as follows:
Bytes sequence order for I2C controller :
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
Byte0,1,2...
until Stop
Set R/W to 1 when read back the data sequence is as follows, [1101 0011] :
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack Byte 1
Ack
Byte2, 3, 4...
until Stop
8.3 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true
power up. Registers are set to the values shown only on true power up. "Command Code" byte and
"Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data
(bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.
After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
Publication Release Date: Dec. 1998
- 8 - Revision 0.20







W83194R-81 equivalent, schematic
W83194R-81
10.0 POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
CPUCLK
(Internal)
12
PCICLK
(Internal)
PCICLK_F
CPU_STOP#
PRELIMINARY
12
CPUCLK[0:3]
SDRAM
For synchronous Chipset, CPU_STOP# pin is a synchronous “active low ”input pin used to stop the
CPU clocks for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU locks on latencyis less than 2 CPU clocks and
locks off latency is less then 2 CPU clocks.
10.2 PCI_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
PCI_STOP#
12
12
PCICLK[0:4]
For synchronous Chipset, PCI_STOP# pin is a synchronous ctive lowinput pin used to stop the
PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output
with full pulse width. In this case, PCI locks on latencyis less than 1 PCI clocks and locks off
latency is less then 1 PCI clocks.
- 16 -
Publication Release Date: Dec. 1998
Revision 0.20










页数 18 页
下载[ W83194R-81.PDF 数据手册 ]


分享链接

Link :

推荐数据表

零件编号描述制造商
W83194R-81100MHZ CLOCK FOR SIS CHIPSETWinbond
Winbond

零件编号描述制造商
STK15C88256-Kbit (32 K x 8) PowerStore nvSRAMCypress Semiconductor
Cypress Semiconductor
NJM4556DUAL HIGH CURRENT OPERATIONAL AMPLIFIERNew Japan Radio
New Japan Radio
EL1118-G5 PIN LONG CREEPAGE SOP PHOTOTRANSISTOR PHOTOCOUPLEREverlight
Everlight


DataSheet8.cn    |   2020   |  联系我们   |   搜索  |  Simemap