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PDF ( 数据手册 , 数据表 ) W83194R-67A

零件编号 W83194R-67A
描述 100MHZ 3-DIMM CLOCK FOR VIA MVP4
制造商 Winbond
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W83194R-67A 数据手册, 描述, 功能
W83194R-67A
100MHZ 3-DIMM CLOCK FOR VIA MVP4
1.0 GENERAL DESCRIPTION
The W83194R-67A is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel Pentium , AMD and Cyrix. W83194R-67A provides sixteen
CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-67AA also
provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.
The W83194R-67A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
Spread spectrum built in at ¡Ó0.5% or ¡Ó0.25% to reduce EMI. Programmable stopping individual
clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up
stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
Supports Pentium, AMD, Cyrix CPU with I2C.
4 CPU clocks (one free-running CPU clock)
13 SDRAM clocks for 3 DIMs
6 PCI synchronous clocks
Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
< 250ps skew among CPU and SDRAM clocks
< 4ns propagation delay SDRAM from buffer input
Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 60 MHz to 124 MHz CPU
I2C 2-Wire serial interface and I2C read back
¡Ó0.25% or ¡Ó0.5% spread spectrum function to reduce EMI
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
2ms power up clock stable time
MODE pin for power Management
One 48 MHz for USB & one 24 MHz for super I/O
48-pin SSOP package
Publication Release Date: Feb. 1999
- 1 - Revision 0.30







W83194R-67A pdf, 数据表
W83194R-67A
Frequency table by I2C
SSEL3 SSEL2 SSEL1
111
111
110
110
101
101
100
100
011
011
010
010
001
001
000
000
PRELIMINARY
SSEL0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
CPU,SDRA
M(MHz)
60
66.8
70
90
80
83.3
95.25
100.2
75
80
83.3
105
110
115
120
124
PCI(MHz)
30(CPU/2)
33.4(CPU/2)
35(CPU/2)
30(CPU/3)
26.67(CPU/3)
27.77(CPU/3)
31.75(CPU/3)
33.3(CPU/3)
37.5(CPU/2)
40(CPU/2)
41.65(CPU/2)
35(CPU/3)
36.67(CPU/3)
38.33(CPU/3)
40(CPU/3)
41.33(CPU/3)
REF,IOAPIC (MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
8.3.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)
Bit @PowerUp Pin
Description
7 x - Latched FS2#
6 1 - Reserved
5 1 - Reserved
4 1 - Reserved
3 1 42 CPUCLK2 (Active / Inactive)
2 1 43 CPUCLK1 (Active / Inactive)
1 1 45 CPUCLK0 (Active / Inactive)
0 1 46 CPUCLK_F (Active / Inactive)
Publication Release Date: Feb. 1999
- 8 - Revision 0.30







W83194R-67A equivalent, schematic
W83194R-67A
11.0 OPERATION OF DUAL FUCTION PINS
PRELIMINARY
Vdd
Device
Pin
Series
10kTerminating
Resistor
Clock
Trace
10k
EMI
Reducing
Cap
Ground
Optional
Ground
Programming Header
Vdd Pad
10k
Device
Pin
Ground Pad
Series
Terminating
Resistor
Clock
Trace
EMI
Reducing
Cap
Optional
Ground
- 16 -
Publication Release Date: Feb. 1999
Revision 0.30










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