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PDF ( 数据手册 , 数据表 ) W83194R-39

零件编号 W83194R-39
描述 100MHZ 3-DIMM CLOCK
制造商 Winbond
LOGO Winbond LOGO 


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W83194R-39 数据手册, 描述, 功能
W83194R-39/-39A
1.0 GENERAL DESCRIPTION
100MHZ 3-DIMM CLOCK
The W83194R-39/-39A is a Clock Synthesizer which provides all clocks required for high-speed RISC
or CISC microprocessor such as Intel Pentium II. W83194R-39 provides eight different frequency of
CPU and PCI clocks and W83194R-39A provides sixteen CPU/PCI frequencies which are externally
selectable with smooth transitions. W83194R-39/-39A also provides 13 SDRAM clocks controlled by
the none-delay buffer_in pin.
The W83194R-39/-39A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. Spread spectrum built in at ¡Ó0.5% or ¡Ó0.25% to reduce EMI. Programmable stopping
individual clock outputs and frequency selection through I2C interface. The device meets the
Pentium power-up stabilization, which requires CPU and PCI clocks be stable within 2 ms after
power-up. It is not recommend to use the dual function pin for the slots(ISA, PCI, CPU, DIMM). The
add on cards may have a pull up or pull down.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
Supports PentiumII CPU with I2C.
2 CPU clocks (one free-running CPU clock)
13 SDRAM clocks for 3 DIMs
6 PCI synchronous clocks
One IOAPIC clock for multiprocessor support
Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
< 250ps skew among CPU and SDRAM clocks
< 250ps skew among PCI clocks
< 5ns propagation delay SDRAM from buffer input
Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.
Smooth frequency switch with selections from 50 MHz to 133 MHz CPU
I2C 2-Wire serial interface and I2C read back
Publication Release Date: May 1998
- 1 - Revision 0.20







W83194R-39 pdf, 数据表
W83194R-39/-39A
PRELIMINARY
8.0 FUNTION DESCRIPTION
8.1 POWER MANAGEMENT FUNCTIONS
All clocks can be individually enabled or disabled via the 2-wire control interface. On power up,
external circuitry should allow 3 ms for the VCO’s to stabilize prior to enabling clock outputs to
assure correct pulse widths. When MODE=0, pins 15 and 46 are inputs (PCI_STOP#),
(CPU_STOP#), when MODE=1, these functions are not available. A particular clock could be
enabled as both the 2-wire serial control interface and one of these pins indicate that it should be
enable.
The W83194R-39/-39Amay be disabled in the low state according to the following table in order to
reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period
on transitions from running to stop. The CPU and PCI clocks transform between running and stop by
waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after
which high levels of the output are either enabled or disabled.
CPU_STOP# PCI_STOP#
00
01
10
11
CPUCLK1,
IOAPIC &
SDRAM 0:12
LOW
LOW
RUNNING
RUNNING
PCI
LOW
RUNNING
LOW
RUNNING
OTHER CLKs
RUNNING
RUNNING
RUNNING
RUNNING
XTAL & VCOs
RUNNING
RUNNING
RUNNING
RUNNING
8.2 2-WIRE I2C CONTROL INTERFACE
The clock generator is a slave I2C component which can be “read backthe data stored in the
latches for verification. All proceeding bytes must be sent to change one of the control bytes. The 2-
wire control interface allows each clock output individually enabled or disabled. On power up, the
W83194R-39/-39Ainitializes with default register settings, and then it’s optional to use the 2-wire
control interface.
The SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK is high
during normal data transfer. There are only two exceptions. One is a high-to-low transition on
SDATA while SDCLK is high used to indicate the beginning of a data transfer cycle. The other is a
low-to-high transition on SDATA while SDCLK is high used to indicate the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes followed by an acknowledge generated.
Byte writing starts with a “startcondition followed by 7-bit slave address and a write command bit
[1101 0010], command code checking [0000 0000], and byte count checking. After successful
reception of each byte, an “acknowledge(low) on the SDATA wire will be generated by the clock
chip. Controller can start to write to internal I2C registers after the string of data. The sequence
order is as follows:
Publication Release Date: May 1998
- 8 - Revision 0.20







W83194R-39 equivalent, schematic
W83194R-39/-39A
PRELIMINARY
9.4.3 TYPE 3 BUFFER FOR REF1, 24MHZ, 48MHZ
Parameter
Symbol Min Typ Max Units
Test Conditions
Pull-Up Current Min
IOH(min) -29
mA Vout = 1.0 V
Pull-Up Current Max
IOH(max)
-23 mA Vout = 3.135V
Pull-Down Current Min
IOL(min)
29
mA Vout = 1.95 V
Pull-Down Current Max
Rise/Fall Time Min
Between 0.8 V and 2.0 V
IOL(max)
TRF(min)
1.0
mA Vout = 0.4 V
ns 10pF Load
Rise/Fall Time Max
Between 0.8 V and 2.0 V
TRF(max)
4.0 ns 20pF Load
9.4.4 TYPE 4 BUFFER FOR SDRAM (0:12)
Parameter
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
Rise/Fall Time Min
Between 0.8 V and 2.0 V
Rise/Fall Time Max
Between 0.8 V and 2.0 V
Symbol
IOH(min)
IOH(max)
IOL(min)
IOL(max)
TRF(min)
Min
0.5
TRF(max)
Typ
Max
-46
53
1.3
Units
Test Conditions
mA Vout = 1.65 V
mA Vout = 3.135 V
mA Vout = 1.65 V
mA Vout = 0.4 V
ns 20pF Load
ns 30pF Load
9.4.5 TYPE 5 BUFFER FOR PCICLK(0:4,F)
Parameter
Pull-Up Current Min
Pull-Up Current Max
Pull-Down Current Min
Pull-Down Current Max
Rise/Fall Time Min
Between 0.8 V and 2.0 V
Rise/Fall Time Max
Between 0.8 V and 2.0 V
Symbol
IOH(min)
IOH(max)
IOL(min)
IOL(max)
TRF(min)
Min
-33
30
0.5
TRF(max)
Typ
Max
-33
38
2.0
Units
Test Conditions
mA Vout = 1.0 V
mA Vout = 3.135 V
mA Vout = 1.95 V
mA Vout = 0.4 V
ns 15pF Load
ns 30pF Load
- 16 -
Publication Release Date: May 1998
Revision 0.20










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