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PDF ( 数据手册 , 数据表 ) W83194R-17

零件编号 W83194R-17
描述 100MHZ AGP CLOCK FOR SIS CHIPSET
制造商 Winbond
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W83194R-17 数据手册, 描述, 功能
W83194R-17/-17A
1.0 GENERAL DESCRIPTION
100MHZ AGP CLOCK FOR SIS CHIPSET
The W83194R-17/-17A is a Clock Synthesizer which provides all clocks required for high-speed RISC
or CISC microprocessor such as Intel PentiumII, PentiumPro , AMD or Cyrix. Eight different
frequency of CPU, AGP and PCI clocks are externally selectable with smooth transitions. The
W83194R-17/-17A provides AGP clocks especially for clone chipset. The highest CPU frequency
provided by the W83194R-17 is up to 100MHz, but the one of W83194R-17A is up to 133MHz.
The W83193R-17/-17A provides I2C serial bus interface to program the registers to enable or disable
each clock outputs and choose the 0.5% or 1.5% center type spread spectrum to reduce EMI.
The W83194R-17/-17A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V
supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate
into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads
as maintaining 50¡Ó5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz
provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
Supports Pentium, PentiumPro, PentiumII, AMD and Cyrix CPUs with I2C.
4 CPU clocks
12 SDRAM clocks for 3 DIMMs
Two AGP clocks
6 PCI synchronous clocks.
Optional single or mixed supply:
(Vdd = Vddq3 = Vddq2 = Vddq2b = 3.3V) or (Vdd =Vddq2 = Vddq3 = 3.3V, Vddq2b = 2.5V)
Skew form CPU to PCI clock -1 to 4 ns, center 2.6 ns, AGP to CPU sync. skew 0 ns (250 ps)
Smooth frequency switch with selections from 60 MHz to 133 MHz CPU
I2C 2-Wire serial interface and I2C read back
¡Ó0.5% or ¡Ó1.5% center type spread spectrum function to reduce EMI
Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
MODE pin for power Management
48 MHz for USB
24 MHz for super I/O
48-pin SSOP package
Publication Release Date: Sep. 1998
- 1 - Revision 0.20







W83194R-17 pdf, 数据表
W83194R-17/-17A
Bytes sequence order for I2C controller :
Clock Address
A(6:0) & R/W
Ack
8 bits dummy
Command code
Ack
8 bits dummy
Byte count
Ack
PRELIMINARY
Byte0,1,2...
until Stop
Set R/W to 1 when read back the data sequence is as follows :
Clock Address
A(6:0) & R/W
Ack
Byte 0
Ack Byte 1
Ack
Byte2, 3, 4...
until Stop
8.3 SERIAL CONTROL REGISTERS
The Pin column lists the affected pin number and the @PowerUp column gives the state at true
power up. Registers are set to the values shown only on true power up. "Command Code" byte and
"Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data
(bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge.
After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and
acknowledged.
8.3.1 Register 0: CPU Frequency Select Register
Bit @PowerUp
70
60
50
40
30
20
10
00
Pin Description
- 0 = ¡Ó1.5% Spread Spectrum Modulation
1 = ¡Ó0.5% Spread Spectrum Modulation
- SSEL2 ( Frequency table selection by software via I2C)
- SSEL1 ( Frequency table selection by software via I2C)
- SSEL0 ( Frequency table selection by software via I2C)
- 0 = Selection by hardware
1 = Selection by software I2C - Bit 6:4
- 0 = Spread Spectrum center spread type
1 = Spread Spectrum down spread type
- 0 = Normal
1 = Spread Spectrum enabled
- 0 = Running
1 = Tristate all outputs
Publication Release Date: Sep. 1998
- 8 - Revision 0.20







W83194R-17 equivalent, schematic
W83194R-17/-17A
10.0 POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
PRELIMINARY
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
CPU_STOP#
CPUCLK[0:3]
12
12
SDRAM
For synchronous Chipset, CPU_STOP# pin is a synchronous active low input pin used to stop the
CPU clocks for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume
output with full pulse width. In this case, CPU “clocks on latencyis less than 2 CPU clocks and
“clocks off latencyis less then 2 CPU clocks.
10.2 PCI_STOP# Timing Diagram
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
PCI_STOP#
1
2
12
PCICLK[0:4]
For synchronous Chipset, PCI_STOP# pin is a synchronous “active lowinput pin used to stop the
PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while
the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output
with full pulse width. In this case, PCI “clocks on latencyis less than 1 PCI clocks and “clocks off
latencyis less then 1 PCI clocks.
- 16 -
Publication Release Date: Sep. 1998
Revision 0.20










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