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PDF ( 数据手册 , 数据表 ) W78E51BF-24

零件编号 W78E51BF-24
描述 8-BIT MTP MICROCONTROLLER
制造商 Winbond
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W78E51BF-24 数据手册, 描述, 功能
Preliminary W78E51B
8-BIT MTP MICROCONTROLLER
GENERAL DESCRIPTION
The W78E51B is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78E51B is fully compatible with the standard 8051.
The W78E51B contains an 4K bytes MTP ROM (Multiple-Time Programmable ROM); a 128 bytes
RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; two 16-bit
timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by
seven sources two-level interrupt capability. To facilitate programming and verification, the MTP-
ROM inside the W78E51B allows the program memory to be programmed and read electronically.
Once the code is confirmed, the user can protect the code for security.
The W78E51B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design 8-bit CMOS microcontroller
Wide supply voltage of 4.5V to 5.5V
128 bytes of on-chip scratchpad RAM
4 KB electrically erasable/programmable MTP-ROM
64 KB program memory address space
64 KB data memory address space
Four 8-bit bi-directional ports
One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
Two 16-bit timer/counters
One full duplex serial port(UART)
Watchdog Timer
seven sources, two-level interrupt capability
EMI reduction mode
Built-in power management
Code protection mechanism
Packages:
DIP 40: W78E51B-24/40
PLCC 44: W78E51BP-24/40
PQFP 44: W78E51BF-24/40
Publication Release Date: December 1998
- 1 - Revision A1







W78E51BF-24 pdf, 数据表
Preliminary W78E51B
Typical Watch-Dog time-out period when OSC = 20 MHz
PS2 PS1 PS0
00 0
01 0
00 1
01 1
10 0
10 1
11 0
11 1
WATCHDOG TIME-OUT PERIOD
19.66 mS
39.32 mS
78.64 mS
157.28 mS
314.57 mS
629.14 mS
1.25 S
2.50 S
Clock
The W78E51B is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78E51B relatively insensitive to duty
cycle variations in the clock. The W78E51B incorporates a built-in crystal oscillator. To make the
oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load
capacitor must be connected from each pin to ground. An external clock source should be connected
to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as
required by the crystal oscillator.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E51B is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
ON-CHIP MTP ROM CHARACTERISTICS
The W78E51B has several modes to program the on-chip MTP-ROM. All these operations are
configured by the pins RST, ALE, PSEN , A9CTRL(P3.0), A13CTRL(P3.1), A14CTRL(P3.2),
OECTRL(P3.3), CE (P3.6), OE (P3.7), A0(P1.0) and VPP( EA ). Moreover, the A15A0(P2.7P2.0,
-8-







W78E51BF-24 equivalent, schematic
Preliminary W78E51B
TIMING WAVEFORMS
Program Fetch Cycle
XTAL1
S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
ALE
PSEN
PORT 2
T APL
T PSW
TAAS
T AAH
T PDA
TALW
TPDH, TPDZ
PORT 0
Code
A0-A7
Data
A0-A7
Code A0-A7
Data
A0-A7
Data Read Cycle
XTAL1
ALE
PSEN
PORT 2
PORT 0
RD
S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3
A0-A7
T DAR
A8-A15
T DDA
DATA
T DDH, T DDZ
T DRD
- 16 -










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