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PDF ( 数据手册 , 数据表 ) W6662CF

零件编号 W6662CF
描述 SCANNER ANALOG FRONT END
制造商 Winbond
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W6662CF 数据手册, 描述, 功能
Preliminary W6662CF
SCANNER ANALOG FRONT END
1. GENERAL DESCRIPTION
The W6662 is a highly integrated CCD/CIS analog front end signal processor. It provides the
components required for all necessary front-end signal process of a CCD/CIS scanner, including a 3-
channel input clamp circuit for correlated double sampling (short as CDS) mode, a multiplexer to mux
3-channel inputs to a correlated double sampling (CDS) circuit, a programmable offset adjusted and
gain controlled amplifier, a 12-bit analog-to-digital converter.
CDS or S&H (sample and hold) of operation modes can be chosen. The device configuration is
programmed via 3-wire or 4-wired interface, operation modes, offset and gain value of each channel
can be programmed.
2. FEATURES
12-bit A/D Converter
No Missing Code Guaranteed
Three channels analog input with clamp circuit individually
Integrated Correlated Double Sampler (CDS)
Supports Contact Image Sensors (CIS)
Accept CCD/CIS sensor with three channel or single channel analog out
External offset voltage input for CIS reference voltage
Built-in bandgap reference circuit for CDS mode and A/D Converter
Integrated 6-bit Programmable Gain Amplifier (PGA) with 3-channel register selected
Integrated 8-bit offset adjustment with 3-channel register selected
3 MHz sampling rate of offset/gain adjustment circuit
Three-wired or four-wired Serial Interface programmable
Registers readback capability
Low power CMOS device
Power down mode supported
3/5V digital I/O pin
Packageed in 48-pin QFP
Applications:
Flatbed Scanners
Sheetfeed Scanners
Film Scanners
Publication Release Date: December 1998
- 1 - Revision A1







W6662CF pdf, 数据表
Preliminary W6662CF
R/W A0 A1 A2 -- -- -- -- D0 D1 D2 D3 D4 D5 D6 D7
Address phase
Data phase
R/W is read (high) or write (low) command to access the register.
A0, A1 and A2 is the address select bits of the register.
D0 throuth D7 is the data bit of the register, D7 is MSB and D0 is LSB.
The address of the registers is:
A2 A1 A0
REGISTER
0 0 0 Configuration Register
0 0 1 Red PGA Register
0 1 0 Green PGA Register
0 1 1 Blue PGA Register
1 0 0 Red Offset Register
1 0 1 Green Offset Register
1 1 0 Blue Offset Register
1 1 1 Reserved
Configuration Register
The bit definition of configuration register is:
A. Configuration mode (wake up and configuration)
bit 0 = 0: 1.5V input span.
1: 3.0V input span.
bit 1 = 0: S&H mode.
1: CDS mode.
bit [3:2] = 0 0: Red channel input only.
0 1: Green channel input only.
1 0: Blue channel input only.
1 1: Three channels input and selected by SEL1 and SEL0 signals.
bit 4 = Reserved (must set to 0).
bit 5 = 0: PAOUT and PAOUTN enable.
1: PAOUT and PAOUTN disable.
bit 6 = Reserved (must set to 0).
bit 7 = 0.
-8-







W6662CF equivalent, schematic
Preliminary W6662CF
8. APPLICATION CIRCUITS
8.1 System Application
Figure 8-1 is the application block diagram of scanner, the photo sensor may be CCD device or CIS
device with single channel or three-channel analog output. The ASIC is used to generate the request
signal of photo sensor, W6662, motor control and other mechanical/electric interface. The memory
buffer is used to temporary store the image data and the data will be transfered to the host through
EPP port or other interface as SCSI. If micro controller is included, some control sequence, photo
sensor calibration or image data procession can be completed without the aid of the host.
to/from
other mechanical
control and senor
Photo
Sensor
W6662
Memory
Buffer
Scanner
ASIC
Host
Interface
Micro
Controller
(optional)
Fig. 8-1 System Application.
- 16 -










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