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PDF ( 数据手册 , 数据表 ) R2000

零件编号 R2000
描述 HIGH VOLTAGE RECTIFIER
制造商 Diodes Incorporated
LOGO Diodes Incorporated LOGO 


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R2000 数据手册, 描述, 功能
R1LV0408C-I Series
Wide Temperature Range Version
4M SRAM (512-kword × 8-bit)
REJ03C0098-0200Z
Rev. 2.00
May.25.2004
Description
The R1LV0408C-I is a 4-Mbit static RAM organized 512-kword × 8-bit. R1LV0408C-I Series has
realized higher density, higher performance and low power consumption by employing CMOS process
technology (6-transistor memory cell). The R1LV0408C-I Series offers low power standby power
dissipation; therefore, it is suitable for battery backup systems. It has packaged in 32-pin SOP, 32-pin
TSOP II and 32-pin STSOP.
Features
Single 3 V supply: 2.7 V to 3.6 V
Access time: 55/70 ns (max)
Power dissipation:
Active: 6 mW/MHz (typ)
Standby: 1.5 µW (typ)
Completely static memory.
No clock or timing strobe required
Equal access and cycle times
Common data input and output.
Three state output
Directly TTL compatible.
All inputs and outputs
Battery backup operation.
Operating temperature: 40 to +85°C
Rev.2.00, May.25.2004, page 1 of 12







R2000 pdf, 数据表
R1LV0408C-I Series
Write Cycle
R1LV0408C-I
-5SI -7LI
Parameter
Symbol Min Max Min Max Unit Notes
Write cycle time
tWC 55 70 ns
Chip selection to end of write
tCW 50 60 ns 4
Address setup time
tAS 0 0 ns 5
Address valid to end of write
tAW 50 60 ns
Write pulse width
tWP 40 50 ns 3, 12
Write recovery time
tWR 0 0 ns 6
Write to output in high-Z
tWHZ 0 20 0 25 ns 1, 2, 7
Data to write time overlap
tDW 25 30 ns
Data hold from write time
tDH 0 0 ns
Output active from end of write
tOW 5 5 ns 2
Output disable to output in high-Z
tOHZ
0
20 0
25 ns 1, 2, 7
Notes: 1. tHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions
and are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS# and a low WE#. A write begins at the later
transition of CS# going low or WE# going low. A write ends at the earlier transition of CS# going
high or WE# going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from CS# going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of WE# or CS# going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8. If the CS# low transition occurs simultaneously with the WE# low transition or after the WE#
transition, the output remain in a high impedance state.
9. Dout is the same phase of the write data of this write cycle.
10. Dout is the read data of next address.
11. If CS# is low during this period, I/O pins are in the output state. Therefore, the input signals of
the opposite phase to the outputs must not be applied to them.
12. In the write cycle with OE# low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention. tWP tDW min + tWHZ max
Rev.2.00, May.25.2004, page 8 of 12














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