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PDF ( 数据手册 , 数据表 ) PC-414SRC

零件编号 PC-414SRC
描述 Last Time Buy Notice Board Products
制造商 ETC
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PC-414SRC 数据手册, 描述, 功能
Last Time Buy Notice – Board Products
November 7, 2003
Effective immediately, DATEL, Inc. will be phasing out its line of board-level data acquisition
products. We will accept last time buy orders until February 28, 2004. Final shipments must
be accepted by June 31, 2004. In addition, all repairs and technical support must be concluded
by September 30, 2004. Please contact DATEL Sales as soon as practical to schedule your
order.
If this Notice is received by Purchasing, Materiel or Procurement personnel, we strongly
encourage you to forward this to your Engineering, Administrative and Program colleagues as
soon as practical.
Models to be Discontinued - Essentially all DATEL board-level data acquisition products, all
board-level accessories and all board software are covered in this Notice. This includes:
All ST-xxx model numbers (Multibus I boards, example ST-711)
All PC-xxx model numbers (ISA bus boards, example PC-414)
All DVME-xxx model numbers (VME bus boards, example DVME-628)
All CPCI-xxx model numbers (Compact PCI bus boards, example CPCI-511)
All PCI-xxx model numbers (PCI bus boards, example PCI-416)
Please note that many older ST-xxx, DVME-xxx and PC-xxx boards are already on very
limited availability due to component obsolescence and other manufacturing issues.
Last Time Orders - Customers should contact the DATEL Sales Dept. (Mansfield, MA, USA)
directly to place orders and negotiate delivery schedules. Some products may require minimum
order quantities and/or extended delivery. This varies over time so it is difficult to give an exact
list of such products.
To assure supply, we encourage customers to accept deliveries as soon as practical. As
time passes, customers risk non-availability of an increasing number of products. After the
customer accepts final order acknowledgement, all orders placed will be firm and non-
cancellable.







PC-414SRC pdf, 数据表
PC-414
®®
SPECIFICATIONS, CONTINUED
(Typical @ +25°C, dynamic conditions, unless noted)
A/D MEMORY
Architecture
Memory Capacity
First-In, First-Out (FIFO)
1024, 4096, or 16,384 A/D
samples. 64 K on request.
TRIGGER CONTROL
Programmable Interval
Timer Type
Functions
Pacer Sample Counter
82C54 Clock Source
Scan Trigger Clock
Analog Trigger Input Range
[Note 5]
Analog Trigger Response
Analog Trigger Hysteresis
82C54
1. A/D sample count reached
2. A/D start rate (16 bit divisor)
3. SSH sample counter (414A)
3 to 65,536 samples. Drives
the Acquire flag/interrupt
gate for A/D start pulses.
Internal 8 MHz crystal clock
125, 250, or 500 KHz
±10 V (not avail. 414D)
2 µs to set status flag
40 mV
ANALOG OUTPUT
Number of Channels
Function
(user-selectable)
[Note 5]
Resolution
Output Voltage Range
(user-selectable)
Linearity
Settling Time
(10 V step)
Input Coding
(user-selectable)
One
1. General purpose analog
output
2. Threshold comparator for
A/D trigger
12 bits
0 to +10 V, ±5 V and ±10 V
at 5 mA max.
±0.05% of FSR
5 microseconds to 0.05%
Same as A/D section
ISA BUS INTERFACE
Architecture
I/O Mapping
Data Transfer
Data Bus
Direct Memory Access
DMA Request Conditions
(software selectable)
Control/Status Functions
I/O mapped, pluggable to
IBM-PC/AT, and compatibles.
Decodes eight 16-bit I/O
registers.
Decodes I/O address lines
A9 - A0
I/O transfer or host DMA,
software selectable
16 bits
1 channel, selectable on
channels 5, 6, or 7, set by
software
FIFO full, half full, not empty,
scan acquire flag (sample
count reached)
Board reset, FIFO flags,
interrupt select and status,
DMA select and status, trigger
source, timer control and
period, sample count load,
parallel outport enable, A/D
enable, MUX auto-sequence
Number of Interrupts
(software selectable)
Bus Interrupt Sources
PARALLEL DATA PORT
1 interrupt, software
selectable on level 7, 9 thru
11, or 15.
Scan acquire flag (sample
count), FIFO full or half full,
DMA terminal count from bus.
Outport Type
Operating Modes
Parallel Port Loading
Parallel Port Connector
Port Data Rate
DIGITAL I/O PORT
16 data output lines, TTL
levels from A/D FIFO.
Includes handshake signals
and FIFO flags. The outport
does not provide addressing.
Asynchoronous master to
external slave receiver. 4
modes are included, offering
internal/external clocking (to
10 MHz), synchronous/
asynchronous handshaking.
Sequencing is compatible
with DT Connect®.
24 mA out, 1.6 mA in. The
data outputs may be tri-stated
for shared bus connection.
2-row 26-pin header type
mounted on board interior.
0.100” pin spacing suitable
for flat cable. Pinout is
compatible with DT Connect®
and existing 414 format.
4 MHz max. Data may be
transferred up to 10 MHz
with external clocking.
Connector
Configuration
Levels
Outport Settling Time
Dual row, 26-pin header
mounted on board interior.
Uses 0.100” pin spacing
suitable for flat cable.
Includes +5 Vdc and digital
ground connections.
8 digital outputs, 8 digital
inputs (unlatched)
Buffered, TTL levels.
10 output loads.
50 ns max. after write operation
MISCELLANEOUS
Analog Section Modularity
Analog Section Adjustments
Analog Input Connectors
The MUX-S/H-A/D module is
socketed for function
interchange.
Offset and gain per channel
for SSH on PC-414F, G, H,
K, M, N, and P. A single
offset and gain pot is
provided on PC-414B, D,
and E. Recommended
recalibration interval is 90
days in stable conditions.
Four SMA miniature coaxial,
mounted on rear slot. [Note 8]
DATEL, Inc., Mansfield, MA 02048 (USA) Tel: (508)339-3000, (800)233-2765 Fax: (508)339-6356 Email: [email protected] Internet: www.datel.com
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