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PDF ( 数据手册 , 数据表 ) QS5LV91970Q

零件编号 QS5LV91970Q
描述 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
制造商 Integrated Device Technology
LOGO Integrated Device Technology LOGO 


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QS5LV91970Q 数据手册, 描述, 功能
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
3.3V LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
INDUSTRIALTEMPERATURERANGE
QS5LV919
FEATURES:
• 3.3V operation
• JEDEC compatible LVTTL level outputs
• Clock inputs are 5V tolerant
• < 300ps output skew, Q0–Q4
• 2xQ output, Q outputs, Q output, Q/2 output
• Outputs 3-state and reset while OE/RST low
• PLL disable feature for low frequency testing
• Internal loop filter RC network
• Functional equivalent to MC88LV915, IDT74FCT388915
• Positive or negative edge synchronization (PE)
• Balanced drive outputs ±24mA
• 160MHz maximum frequency (2xQ output)
• Available in QSOP and PLCC packages
DESCRIPTION:
The QS5LV919 Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to one of two reference clock inputs.
Eight outputs are available: 2xQ, Q0-Q4, Q5, Q/2. Careful layout and
design ensure < 300 ps skew between the Q0-Q4, and Q/2 outputs.
The QS5LV919 includes an internal RC filter which provides excellent
jitter characteristics and eliminates the need for external components.
Various combinations of feedback and a divide-by-2 in the VCO path
allow applications to be customized for linear VCO operation over a
wide range of input SYNC frequencies. The PLL can also be disabled
by the PLL_EN signal to allow low frequency or DC testing. The LOCK
output asserts to indicate when phase lock has been achieved. The
QS5LV919 is designed for use in high-performance workstations, multi-
board computers, networking hardware, and mainframe systems. Sev-
eral can be used in parallel or scattered throughout a system for guar-
anteed low skew, system-wide clock distribution networks.
For more information on PLL clock driver products, see Application
Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
O E /R S T
SYNC0
SYNC1
REF_SEL
0
LOCK PE
FEEDBACK
1
PHASE
LOOP
DETECTOR
FILTER
VCO
PLL_EN
FREQ_SEL
01
1 /2 0
RDR DR DRDR DR DRD
Q Q Q Q Q Q QQ
Q /2 Q5 Q4 Q3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c 2001 Integrated Device Technology, Inc.
1
Q2
Q1 Q0
2xQ
JULY 2001
DSC-5820/3







QS5LV91970Q pdf, 数据表
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIALTEMPERATURERANGE
The frequency relationship shown here is applicable to all Q outputs (Q0, Q1,
Q2, Q3 and Q4).
25 MHz feedback signal
50 MHz signal
2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Inthisapplication,the2QoutputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of 2Q and SYNC, thus the 2Q
frequency will equal the SYNC frequency. The Q/2 output will always run at
1/4 the 2Q frequency, and the Q output will run at 1/2 the 2Q frequency.
Note that with 2Q as feedback, the maximum input frequency is 100MHz for FS
= HIGH
LOW
25 MHz
input
HIGH
OE/RST Q5
FEEDBACK
Q4
REF_SEL
SYNC(0)
VCC(AN)
QS5LV919
PE
2Q
Q/2
12.5 MHz
signal
Q3 25 MHz
"Q"
Clock
Q2 Outputs
50 MHz feedback signal
HIGH
GND(AN)
FQ_SEL
Q0
Q1 PLL_EN
LOW
50 MHz
input
OE/RST Q5
FEEDBACK
Q4
REF_SEL
SYNC(0)
VCC(AN)
PE
QS5LV919
GND(AN)
2Q
Q/2
12.5 MHz
input
Q3 25 MHz
"Q"
Clock
O u tp u ts
Q2
HIGH
HIGH
Allowable Input Frequency Range:
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)
10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)
Figure 2b. Wiring Diagram and Frequency Relationships with
Q4 Output Feedback
FQ_SEL
Q0
HIGH
Q1 PLL_EN
HIGH
Allowable Input Frequency Range:
40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)
20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)
Figure 2a. Wiring Diagram and Frequency Relationships with 2Q
Output Feedback
1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Inthisapplication,theQ4outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q4 and SYNC, thus the Q4
frequency(andtherestofthe"Q"outputs)willequaltheSYNCfrequency. The
Q/2 output will always run at 1/2 the Q frequency, and the 2Q output will run
at 2X the Q frequency.
1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP
Inthisapplication,theQ/2outputisconnectedtotheFEEDBACKinput. The
internal PLL will line up the positive edges of Q/2 and SYNC, thus the Q/2
frequency will equal the SYNC frequency. The Q outputs (Q0-Q4, Q5) will
always run at 2X the Q/2 frequency, and the 2Q output will run at 4X the Q/2
frequency.
50 MHz signal
12.5 MHz feedback signal
HIGH
LOW
12.5 MHz
input
OE/RST Q5
FEEDBACK
Q4 2Q
Q/2
REF_SEL
SYNC(0)
Q3
VCC(AN)
QS5LV919
PE Q2
GND(AN)
FQ_SEL
Q0
Q1 PLL_EN
25 MHz
"Q"
Clock
Outputs
HIGH
HIGH
Allowable Input Frequency Range:
10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)
5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)
Figure 2c. Wiring Diagram and Frequency Relationships with
Q2 Output Feedback
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